| bibtype |
E -
Electronic Document
|
| ARLID |
0079768 |
| utime |
20240111140646.6 |
| mtime |
20070302235959.9 |
| title
(primary) (cze) |
Reed Solomonův kodér a dekodér pro FPGA |
| publisher |
| place |
Praha |
| name |
ÚTIA AV ČR |
| pub_time |
2007 |
|
| specification |
|
| title
(eng) |
Reed Solomon coder and decoder for FPGA |
| keyword |
FPGA |
| keyword |
RS coder |
| keyword |
Handel C |
| author
(primary) |
| ARLID |
cav_un_auth*0101105 |
| name1 |
Heřmánek |
| name2 |
Antonín |
| institution |
UTIA-B |
| fullinstit |
Ústav teorie informace a automatizace AV ČR, v. v. i. |
|
| author
|
| ARLID |
cav_un_auth*0019600 |
| name1 |
Dušek |
| name2 |
J. |
| country |
CZ |
|
| source |
| source_type |
program |
| source_size |
12,8 MB |
|
| COSATI |
09G |
| COSATI |
09H |
| cas_special |
| project |
| project_id |
1ET100750408 |
| agency |
GA AV ČR |
| ARLID |
cav_un_auth*0001794 |
|
| research |
CEZ:AV0Z10750506 |
| abstract
(cze) |
Tento dokument popisuje základní vlastnosti a parametry IP maker pro implementaci Reed Solomonova (RS) kodéru a dekodéru, které byly imlementovány v jazyce Handel-C na obvodech ALTERA Cyclon EP1C12Q240C8 a odzkoušeny na vývojové desce UP2 a UP3-1C12. |
| abstract
(eng) |
This document presents the parameters and demo application for the Reed Solomon coder and decoder IP macros for the Altera FPGA. The coder and two variants of decoder (serial and parallel versions) are presented. Both, coder and decoder, has been implemented on Altera Cyclon EP1C12Q240C8 device and tested on UP3 evaluation board. |
| reportyear |
2007 |
| RIV |
JC |
| permalink |
http://hdl.handle.net/11104/0144339 |
| arlyear |
2007 |
| mrcbU10 |
2007 |
| mrcbU10 |
Praha ÚTIA AV ČR |
| mrcbU56 |
program 12,8 MB |
|