| bibtype |
E -
Electronic Document
|
| ARLID |
0079825 |
| utime |
20240111140646.6 |
| mtime |
20070302235959.9 |
| title
(primary) (cze) |
Částečná dynamická rekonfigurace na FPGA obvodech firmy XILINX |
| publisher |
| place |
Praha |
| name |
ÚTIA AV ČR |
| pub_time |
2007 |
|
| specification |
|
| title
(eng) |
Partial Dynamic Reconfiguration in Xilinx FPGA Circuits |
| keyword |
FPGA |
| keyword |
dynamic reconfiguration |
| keyword |
Virtex II |
| author
(primary) |
| ARLID |
cav_un_auth*0225749 |
| name1 |
Kohout |
| name2 |
Lukáš |
| institution |
UTIA-B |
| full_dept |
Department of Signal Processing |
| fullinstit |
Ústav teorie informace a automatizace AV ČR, v. v. i. |
|
| source |
| source_type |
program |
| source_size |
35,4 MB |
|
| COSATI |
09G |
| COSATI |
09H |
| cas_special |
| project |
| project_id |
1M0567 |
| agency |
GA MŠk |
| country |
CZ |
| ARLID |
cav_un_auth*0202350 |
|
| project |
| project_id |
027611 |
| agency |
EC |
| country |
XE |
| agency |
EC |
| ARLID |
cav_un_auth*0225974 |
|
| project |
| project_id |
FP6-IST-027611 |
| agency |
EC |
| ARLID |
cav_un_auth*0225974 |
|
| research |
CEZ:AV0Z10750506 |
| abstract
(cze) |
Obsahem tohoto dokumentu je popis aplikace využívající částečné dynamické rekonfigurace na obvodech FPGA firmy Xilinx. Implementován je FIR filtr na ML402 desce firmy Xilinx. |
| abstract
(eng) |
This application note describes the use of the partial dynamic reconfiguration in Xilinx FPGA circuits. The FIR filter is implemented in Xilinx ML402 evaluation platform. |
| reportyear |
2007 |
| RIV |
JC |
| permalink |
http://hdl.handle.net/11104/0144373 |
| arlyear |
2007 |
| mrcbU10 |
2007 |
| mrcbU10 |
Praha ÚTIA AV ČR |
| mrcbU56 |
program 35,4 MB |
|