| bibtype |
E -
Electronic Document
|
| ARLID |
0080727 |
| utime |
20240111140646.8 |
| mtime |
20070326235959.9 |
| title
(primary) (cze) |
PicoBlaze lekce 2: generování VHDL a implementace systému s procesorem PicoBlaze do FPGA v prostředí Xilinx ISE |
| publisher |
| place |
Praha |
| name |
ÚTIA AV ČR |
| pub_time |
2007 |
|
| specification |
|
| title
(eng) |
PicoBlaze lesson 2: Creation and implementation of PicoBlaze-based system in FPGA using Xilinx ISE |
| keyword |
FPGA |
| keyword |
PicoBlaze processor |
| keyword |
integrated circuit |
| keyword |
VHDL |
| author
(primary) |
| ARLID |
cav_un_auth*0225751 |
| name1 |
Stejskal |
| name2 |
Jaroslav |
| institution |
UTIA-B |
| fullinstit |
Ústav teorie informace a automatizace AV ČR, v. v. i. |
|
| author
|
| ARLID |
cav_un_auth*0202863 |
| name1 |
Kafka |
| name2 |
Leoš |
| institution |
UTIA-B |
| fullinstit |
Ústav teorie informace a automatizace AV ČR, v. v. i. |
|
| author
|
| ARLID |
cav_un_auth*0101120 |
| name1 |
Kadlec |
| name2 |
Jiří |
| institution |
UTIA-B |
| full_dept |
Department of Signal Processing |
| fullinstit |
Ústav teorie informace a automatizace AV ČR, v. v. i. |
|
| source |
| source_type |
program |
| source_size |
13 MB |
|
| COSATI |
09H |
| cas_special |
| project |
| project_id |
2C06008 |
| agency |
GA MŠk |
| ARLID |
cav_un_auth*0217826 |
|
| research |
CEZ:AV0Z10750506 |
| abstract
(cze) |
Tato zpráva popisuje druhou lekci ze série lekcí, zabývajících se procesorem PicoBlaze. Tato lekce ukáže postup, jak pomocí jazyka VHDL vytvořit jednoduchý systém s procesorem PicoBlaze. Systém bude složen z procesoru, jeho programové paměti a jednoduchých periferií. Dále bude vysvětlen postup konfigurace FPGA a ověření funkce obvodu v přípravku. |
| abstract
(eng) |
This application note is the second lesson of the course that deals with PicoBlaze processor. It explains how to create a PicoBlaze-based design using VHDL language. The example design is composed of the PicoBlaze processor, instruction memory and several simple peripheral devices. The configuration of FPGA and test of the design in development board is also described. |
| reportyear |
2007 |
| RIV |
JC |
| permalink |
http://hdl.handle.net/11104/0144817 |
| arlyear |
2007 |
| mrcbU10 |
2007 |
| mrcbU10 |
Praha ÚTIA AV ČR |
| mrcbU56 |
program 13 MB |
|