| bibtype |
C -
Conference Paper (international conference)
|
| ARLID |
0085945 |
| utime |
20240103184436.5 |
| mtime |
20070919235959.9 |
| title
(primary) (eng) |
RLS Lattice Algorithm with Order Probability Evaluation as an Accelerator |
| specification |
|
| serial |
| ARLID |
cav_un_epca*0085944 |
| ISBN |
978-1-4244-1059-0 |
| ISBN |
1-4244-1060-6 |
| title
|
Proceedings 2007 International Conference on Field Programmable Logic and Applications (FPL) |
| page_num |
774-777 |
| publisher |
| place |
Delft |
| name |
IEEE |
| year |
2007 |
|
| editor |
|
| editor |
|
| editor |
| name1 |
Genderen |
| name2 |
Arjan |
|
| editor |
| name1 |
Vassiliadis |
| name2 |
Stamatis |
|
|
| title
(cze) |
RLS Lattice rozšířený o odhad pravěpodobnosti řádu jako akcelerátor |
| keyword |
DSP |
| keyword |
adaptive filter |
| keyword |
logarithmic arithmetic |
| keyword |
embedded processor |
| keyword |
FPGA |
| author
(primary) |
| ARLID |
cav_un_auth*0101179 |
| name1 |
Pohl |
| name2 |
Zdeněk |
| institution |
UTIA-B |
| full_dept |
Department of Signal Processing |
| fullinstit |
Ústav teorie informace a automatizace AV ČR, v. v. i. |
|
| author
|
| ARLID |
cav_un_auth*0101213 |
| name1 |
Tichý |
| name2 |
Milan |
| institution |
UTIA-B |
| fullinstit |
Ústav teorie informace a automatizace AV ČR, v. v. i. |
|
| cas_special |
| project |
| project_id |
1M0567 |
| agency |
GA MŠk |
| country |
CZ |
| ARLID |
cav_un_auth*0202350 |
|
| project |
| project_id |
027611 |
| agency |
EC |
| country |
XE |
| agency |
EC |
| ARLID |
cav_un_auth*0225974 |
|
| research |
CEZ:AV0Z10750506 |
| abstract
(eng) |
A high performance RLS lattice filter with evaluation of an unknown order of identified system was implemented as an accelerator for the Microblaze processor. The accelerator hardware can fully exploit parallelisms in the algorithm and remove load from a microprocessor. The optimal logarithmic number system implementation of the RLS lattice IP core was used. The solution makes possible evaluation of the RLS lattice filter of order 256 at 8 kHz sampling rate in the best case. The implementation outperforms software solution up to 74 times and it is also performing 40% faster than other known solutions. |
| abstract
(cze) |
Článek se zabývá implementací adaptivního filtru RLS lattice a jeho využitím jako akcelerátor vestavěného procesoru Microblaze. Takový akcelerátor je schopen využít paralelismu v RLS algoritmu a sejmout tak zátěž z procesoru. Pro implementaci filtru byla použita logaritmická aritmetika. Výsledné řešení umožňuje implementovat adaptivní filtr řádu až 256 pracující s vzorkovací frekvencí 8 kHz, což představuje 74-násobné zrychlení oproti řešení využívající pouze procesor. |
| action |
| ARLID |
cav_un_auth*0230086 |
| name |
International Conference on Field Programmable Logic and Applications. FPL 2007 |
| place |
Amsterdam |
| dates |
27.08.2007-29.08.2007 |
| country |
NL |
|
| reportyear |
2010 |
| RIV |
JC |
| permalink |
http://hdl.handle.net/11104/0004135 |
| arlyear |
2007 |
| mrcbU63 |
cav_un_epca*0085944 Proceedings 2007 International Conference on Field Programmable Logic and Applications (FPL) 978-1-4244-1059-0 774 777 Delft IEEE 2007 07EX1708C |
| mrcbU67 |
Bertels Koen 340 |
| mrcbU67 |
Najjar Walid 340 |
| mrcbU67 |
Genderen Arjan 340 |
| mrcbU67 |
Vassiliadis Stamatis 340 |
|