bibtype	C - Conference Paper (international conference)
ARLID	0091798
utime	20240103184946.6
mtime	20071210235959.9
title (primary) (eng)	Preservation of Circuit Structure and Timing during Fault Emulation in FPGA
specification	page_count 5 s.
serial	ARLID cav_un_epca*0091797 title IP 07 IP Based Electronic System Conference & Exhibition Proceedings page_num 493-497 publisher place Grenoble name EETimes Network year 2007 editor name1 Saucier name2 Gabriele editor name1 Nguyen name2 Huy-Nam
title (cze)	Zachování struktury a časování obvodu při emulaci poruch pomocí FPGA
keyword	Fault emulation
keyword	runtime reconfiguration
keyword	FPGA
author (primary)	ARLID cav_un_auth*0202863 name1 Kafka name2 Leoš institution UTIA-B fullinstit Ústav teorie informace a automatizace AV ČR, v. v. i.
author	ARLID cav_un_auth*0101077 name1 Daněk name2 Martin institution UTIA-B fullinstit Ústav teorie informace a automatizace AV ČR, v. v. i.
author	ARLID cav_un_auth*0045825 name1 Novák name2 O. country CZ
cas_special	project project_id 1QS108040510 agency GA AV ČR country CZ ARLID cav_un_auth*0202864 research CEZ:AV0Z10750506 abstract (eng) This paper presents a technique that allows to preserve structure of a circuit according to a target technology during fault emulation in FPGA. The technique is not restricted to any target technology or FPGA emulation platform. It is compatible with fault injection techniques based both on circuit instrumentation and partial runtime reconfiguration. An extension of this technique that allows to emulate timing parameters of the circuit through an introduction of a virtual time is also proposed. An area and timing overhead due to preserving the circuit structure and parameters of basic delay elements are evaluated by experiments. abstract (cze) Tento článek popisuje metodu, která umožňuje zachovat strukturu emulovaného obvodu s ohledem na cílovou technologii při emulaci poruch pomocí FPGA. Metodu lze použít pro libovolnou cílovou technologii a libovolné FPGA. Metoda umožňuje použít pro vkládání poruch jak metody založené na modifikaci obvodu, tak metody založené na částečné dynamické rekonfiguraci. Metoda dále umožňuje emulovat zpoždění v obvodu pomocí virtuálního času. Základní parametry metody byly vyhodnoceny pomocí několika experimentů. action ARLID cav_un_auth*0234115 name IP 07 IP Based Electronic System Conference & Exhibition place Grenoble dates 05.12.2007-06.12.2007 country FR reportyear 2008 RIV JC permalink http://hdl.handle.net/11104/0152308 arlyear 2007 mrcbU63 cav_un_epca*0091797 IP 07 IP Based Electronic System Conference & Exhibition Proceedings 493 497 Grenoble EETimes Network 2007 mrcbU67 Saucier Gabriele 340 mrcbU67 Nguyen Huy-Nam 340