| bibtype |
A -
Abstract
|
| ARLID |
0092657 |
| utime |
20240103185035.2 |
| mtime |
20071217235959.9 |
| title
(primary) (eng) |
Configuration System for a DSP/FPGA-Based Embedded Accelerator |
| specification |
|
| serial |
| ARLID |
cav_un_epca*0092656 |
| title
|
Digital Technologies 2007 Book of Abstracts |
| page_num |
32-33 |
| publisher |
| place |
Žilina |
| name |
Slovenská elektrotechnická spoločnosť |
| year |
2007 |
|
| editor |
|
|
| title
(cze) |
Konfigurační systém pro vestavěný DSP/FPGA akcelerátor |
| keyword |
FPGA |
| keyword |
video-processing |
| keyword |
accelerator |
| keyword |
configuration |
| keyword |
Simulink |
| author
(primary) |
| ARLID |
cav_un_auth*0101190 |
| name1 |
Schier |
| name2 |
Jan |
| institution |
UTIA-B |
| full_dept |
Department of Image Processing |
| fullinstit |
Ústav teorie informace a automatizace AV ČR, v. v. i. |
|
| author
|
| ARLID |
cav_un_auth*0101136 |
| name1 |
Kovář |
| name2 |
Bohumil |
| institution |
UTIA-B |
| fullinstit |
Ústav teorie informace a automatizace AV ČR, v. v. i. |
|
| author
|
| ARLID |
cav_un_auth*0202610 |
| name1 |
Zemčík |
| name2 |
P. |
| country |
CZ |
|
| author
|
| ARLID |
cav_un_auth*0202611 |
| name1 |
Herout |
| name2 |
A. |
| country |
CZ |
|
| author
|
| ARLID |
cav_un_auth*0232988 |
| name1 |
Zuzaňák |
| name2 |
J. |
| country |
CZ |
|
| cas_special |
| project |
| project_id |
1ET400750408 |
| agency |
GA AV ČR |
| ARLID |
cav_un_auth*0001798 |
|
| research |
CEZ:AV0Z10750506 |
| abstract
(eng) |
An embedded configuration engine for a DSP/FPGA based accelerator is considered. The engine is used to simplify configuration of the accelerator using ready-made functional blocks. A parser for Simulink models has been designed which generates scripts for the configuration engine as its output. |
| abstract
(cze) |
Článek se zabývá konfiguračním procesorem pro vestavný DSP/FPGA akcelerátor. Konfigurační procesor zjednodušuje, při použití předpřipravených funkčních bloků, konfiguraci akcelerátoru. Článek se zaměřuje především na parser Simulinkových modelů, jehož účelem je generovat z těchto modelů skripty pro konfigurační procesor. |
| action |
| ARLID |
cav_un_auth*0234636 |
| name |
Digital Technologies 2007 |
| place |
Žilina |
| dates |
30.11.2007 |
| country |
SK |
|
| reportyear |
2008 |
| RIV |
JB |
| permalink |
http://hdl.handle.net/11104/0152919 |
| arlyear |
2007 |
| mrcbU63 |
cav_un_epca*0092656 Digital Technologies 2007 Book of Abstracts 32 33 Žilina Slovenská elektrotechnická spoločnosť 2007 |
| mrcbU67 |
Jarina Roman 340 |
|