| bibtype |
L -
Prototype, methodology, f. module, software
|
| ARLID |
0093182 |
| utime |
20240103185106.4 |
| mtime |
20080104235959.9 |
| title
(primary) (cze) |
Akcelerátor pro výpočet odezvy ADSL vedení |
| publisher |
|
| title
(eng) |
Accelerator for computation ADSL line response |
| keyword |
FPGA |
| keyword |
ADSL |
| keyword |
Accelerator |
| keyword |
FIR |
| keyword |
Ethernet |
| author
(primary) |
| ARLID |
cav_un_auth*0225750 |
| name1 |
Kloub |
| name2 |
Jan |
| institution |
UTIA-B |
| fullinstit |
Ústav teorie informace a automatizace AV ČR, v. v. i. |
|
| author
|
| ARLID |
cav_un_auth*0101105 |
| name1 |
Heřmánek |
| name2 |
Antonín |
| institution |
UTIA-B |
| fullinstit |
Ústav teorie informace a automatizace AV ČR, v. v. i. |
|
| cas_special |
| project |
| project_id |
1ET300750402 |
| agency |
GA AV ČR |
| ARLID |
cav_un_auth*0001795 |
|
| research |
CEZ:AV0Z10750506 |
| abstract
(cze) |
Dokument popisuje implementaci akcelerátoru pro výpočet odezvy ADSL vedení na obvodu FPGA. |
| abstract
(eng) |
Document describes implementation of accelerator for computation ADSL line response on FPGA. |
| reportyear |
2008 |
| RIV |
JC |
| permalink |
http://hdl.handle.net/11104/0153293 |
| arlyear |
2007 |
| mrcbU10 |
2007 |
|