| bibtype |
C -
Conference Paper (international conference)
|
| ARLID |
0106325 |
| utime |
20240111140605.3 |
| mtime |
20050527235959.9 |
| title
(primary) (eng) |
Architecture design for FPGA implementation of finite interval CMA |
| specification |
| page_count |
4 s. |
| media_type |
CD-ROM |
|
| serial |
| ISBN |
3-200-00165-8 |
| title
|
Proceedings of the 12th European Signal Processing Conference |
| page_num |
1-4 |
| publisher |
| place |
Vienna |
| name |
University of Technology |
| year |
2004 |
|
| editor |
|
| editor |
|
| editor |
|
|
| title
(cze) |
Návrh architektury pro FPGA implementaci blokového CMA algoritmu (Finite interval CMA) |
| keyword |
blind equalization |
| keyword |
CMA, FPGA |
| keyword |
logarithmic arithmetic |
| author
(primary) |
| ARLID |
cav_un_auth*0101105 |
| name1 |
Heřmánek |
| name2 |
Antonín |
| institution |
UTIA-B |
| fullinstit |
Ústav teorie informace a automatizace AV ČR, v. v. i. |
|
| author
|
| ARLID |
cav_un_auth*0101190 |
| name1 |
Schier |
| name2 |
Jan |
| institution |
UTIA-B |
| full_dept |
Department of Image Processing |
| fullinstit |
Ústav teorie informace a automatizace AV ČR, v. v. i. |
|
| author
|
| ARLID |
cav_un_auth*0021102 |
| name1 |
Regalia |
| name2 |
P. |
| country |
FR |
|
| source |
|
| COSATI |
09J |
| cas_special |
| project |
| project_id |
LN00B096 |
| agency |
GA MŠk |
| ARLID |
cav_un_auth*0027922 |
|
| project |
| project_id |
1ET300750402 |
| agency |
GA AV ČR |
| ARLID |
cav_un_auth*0001795 |
|
| project |
| project_id |
1ET400750408 |
| agency |
GA AV ČR |
| ARLID |
cav_un_auth*0001798 |
|
| research |
CEZ:AV0Z1075907 |
| abstract
(eng) |
In the paper, we present the architecture design of the Finite Interval Constant Modulus Algorithm (FI-CMA) for FPGA implementation. For floating point calculations required in the algorithm we use the library based on the Logarithmic Number System (LNS). In the design, the resource reuse and minimization of the total latency is emphasized. |
| abstract
(cze) |
V článku je prezentován návrh architektury pro FPGA implementaci blokového CMA algoritmu. Pro výpočty v plovoucí řádové čárce, požadované v tomto algoritmu, byla použita aritmetická knihovna využívající logaritmickou číselnou soustavu. Návrh architektury je optimalizován pro vícenásobné využití HW prostředků a minimalizaci celkové latence |
| action |
| ARLID |
cav_un_auth*0129893 |
| name |
EUSIPCO 2004 /12./ |
| place |
Vienna |
| dates |
06.09.2004-10.09.2004 |
| country |
AT |
|
| reportyear |
2005 |
| RIV |
BD |
| permalink |
http://hdl.handle.net/11104/0013507 |
| ID_orig |
UTIA-B 20040137 |
| arlyear |
2004 |
| mrcbU56 |
250 kB |
| mrcbU63 |
Proceedings of the 12th European Signal Processing Conference 3-200-00165-8 1 4 Vienna University of Technology 2004 |
| mrcbU67 |
Hlawatsch F. 340 |
| mrcbU67 |
Matz G. 340 |
| mrcbU67 |
Rupp M. 340 |
|