bibtype C - Conference Paper (international conference)
ARLID 0309238
utime 20240103190137.8
mtime 20080708235959.9
title (primary) (eng) Proposed architecture of configurable, adaptable SoC
specification
page_count 6 s.
serial
ARLID cav_un_epca*0309237
ISBN 978-0-86341-931-7
title The IET Irish Signals and Systems Conference ISSC 2008
page_num 368-373
publisher
place Londýn
name Institution of Engineering and Technology
year 2008
editor
name1 Morgan
name2 Fearghal
editor
name1 Glavin
name2 Martin
editor
name1 Jones
name2 Edward
title (cze) Návrh architektury pro rekonfigurovatelné a adaptovatelné systémy na jednom čipu
keyword MicroBlaze
keyword PicoBlaze
keyword floating point accelerators
keyword runtime reconfiguration
author (primary)
ARLID cav_un_auth*0101120
name1 Kadlec
name2 Jiří
institution UTIA-B
full_dept Department of Signal Processing
fullinstit Ústav teorie informace a automatizace AV ČR, v. v. i.
author
ARLID cav_un_auth*0101077
name1 Daněk
name2 Martin
institution UTIA-B
fullinstit Ústav teorie informace a automatizace AV ČR, v. v. i.
author
ARLID cav_un_auth*0225749
name1 Kohout
name2 Lukáš
institution UTIA-B
full_dept Department of Signal Processing
fullinstit Ústav teorie informace a automatizace AV ČR, v. v. i.
cas_special
project
project_id 2C06008
agency GA MŠk
ARLID cav_un_auth*0217826
project
project_id 027611
agency EC
country XE
agency EC
ARLID cav_un_auth*0225974
research CEZ:AV0Z10750506
abstract (eng) To study the concept of Self Adaptive Networked computing Elements (SANE) we developed a configurable platform based on the Xilinx EDK and Xilinx System Generator tools. The platform is built around a MicroBlaze CPU with a set of standard peripherals such as DDR RAM controller and RS232 interface – denoted as Master, extended with a set of several reprogrammable Accelerators connected to the MicroBlaze Master via fast simplex links (FSL).
abstract (cze) Pro studium SANE jsme navrhli konfigurovatelnou platformu, která kombinuje procesor MicroBlaze a sadu rekonfigurovatelných akcelerátorů připojených pomocí FSL linek na jediném FPGA obvodu.
action
ARLID cav_un_auth*0240335
name The Institution of Engineering and Technology Irish Signals and Systems Conference, ISSC 2008
place Galway
dates 18.06.2008-19.06.2008
country IE
reportyear 2009
RIV JC
permalink http://hdl.handle.net/11104/0161437
arlyear 2008
mrcbU63 cav_un_epca*0309237 The IET Irish Signals and Systems Conference ISSC 2008 978-0-86341-931-7 368 373 Londýn Institution of Engineering and Technology 2008
mrcbU67 Morgan Fearghal 340
mrcbU67 Glavin Martin 340
mrcbU67 Jones Edward 340