| bibtype |
C -
Conference Paper (international conference)
|
| ARLID |
0309834 |
| utime |
20240111140703.5 |
| mtime |
20080717235959.9 |
| title
(primary) (eng) |
Design Flow for Reconfigurable MicroBlaze Accelerators |
| specification |
| page_count |
8 s. |
| media_type |
CD ROM |
|
| serial |
| ARLID |
cav_un_epca*0309833 |
| ISBN |
978-84-691-3603-4 |
| title
|
4th International Workshop on Reconfigurable Communication Centric System-on-Chips Workshop Proceedings |
| page_num |
133-140 |
| publisher |
| place |
Barcelona |
| name |
UPC |
| year |
2008 |
|
| editor |
| name1 |
Moreno |
| name2 |
Manuel J. |
|
| editor |
| name1 |
Madrenas |
| name2 |
Jordi |
|
| editor |
| name1 |
Sassatelli |
| name2 |
Gilles |
|
| editor |
| name1 |
Hübner |
| name2 |
Michael |
|
| editor |
|
|
| title
(cze) |
Návrh rekonfigurovatelných akcelerátorů pro procesor MicroBlaze |
| keyword |
FPGA |
| keyword |
MicroBlaze accelerator |
| keyword |
run-time reconfiguration |
| author
(primary) |
| ARLID |
cav_un_auth*0101120 |
| name1 |
Kadlec |
| name2 |
Jiří |
| institution |
UTIA-B |
| full_dept |
Department of Signal Processing |
| fullinstit |
Ústav teorie informace a automatizace AV ČR, v. v. i. |
|
| source |
| source_type |
textový soubor |
|
| cas_special |
| project |
| project_id |
1M0567 |
| agency |
GA MŠk |
| country |
CZ |
| ARLID |
cav_un_auth*0202350 |
|
| research |
CEZ:AV0Z10750506 |
| abstract
(eng) |
We present design flow and related tool-chain supporting modeling, HW-SW co-simulation as well as generation of HDL code for reconfigurable MicroBlaze accelerators. Each accelerator is composed from reprogrammable PicoBlaze sequencing HW supported floating point processing batches executed on local data. The Xilinx MicroBlaze soft-core processor serves as the central CPU with access to the global off chip memory and peripherals. Each coprocessor can be re-programmed during runtime. This provides a framework for a partial dynamic change of the functionality of HW floating point accelerators suitable for FPGA as well as for the custom designs. |
| abstract
(cze) |
Článek presentuje metodologii návrhu rekonfigurovatelných akcelerátorů pro FPGA procesor MicroBlaze. Každý akcelerátor může být modifikován za chodu pomocí mikroprogramu. |
| action |
| ARLID |
cav_un_auth*0240700 |
| name |
ReCoSoC 2008 4th Reconfigurable Communication-centric Systems-on-Chip workshop |
| place |
Barcelona |
| dates |
09.07.2008-11.07.2008 |
| country |
ES |
|
| reportyear |
2009 |
| RIV |
JC |
| permalink |
http://hdl.handle.net/11104/0161864 |
| arlyear |
2008 |
| mrcbU56 |
textový soubor |
| mrcbU63 |
cav_un_epca*0309833 4th International Workshop on Reconfigurable Communication Centric System-on-Chips Workshop Proceedings 978-84-691-3603-4 133 140 Barcelona UPC 2008 |
| mrcbU67 |
Moreno Manuel J. 340 |
| mrcbU67 |
Madrenas Jordi 340 |
| mrcbU67 |
Sassatelli Gilles 340 |
| mrcbU67 |
Hübner Michael 340 |
| mrcbU67 |
Zipf Peter 340 |
|