| bibtype |
C -
Conference Paper (international conference)
|
| ARLID |
0312223 |
| utime |
20240111140706.1 |
| mtime |
20090326235959.9 |
| WOS |
000256936300025 |
| title
(primary) (eng) |
Fast Boolean Minimizer for Completely Specified Functions |
| specification |
| page_count |
6 s. |
| media_type |
www |
|
| serial |
| ARLID |
cav_un_epca*0312222 |
| ISBN |
978-1-4244-2276-0 |
| title
|
Proc. of 11th IEEE Design and Diagnostics of Electronic Circuits and Systems Workshop 2008 |
| page_num |
122-127 |
| publisher |
| place |
Los Alamitos |
| name |
IEEE |
| year |
2008 |
|
|
| title
(cze) |
Rychlá minimalizace kompletně zadaných logických funkcí |
| keyword |
boolean function |
| keyword |
minimalization |
| keyword |
binary decision diagram |
| author
(primary) |
| ARLID |
cav_un_auth*0242310 |
| name1 |
Fišer |
| name2 |
P. |
| country |
CZ |
|
| author
|
| ARLID |
cav_un_auth*0242311 |
| name1 |
Rucký |
| name2 |
P. |
| country |
CZ |
|
| author
|
| ARLID |
cav_un_auth*0217879 |
| name1 |
Váňová |
| name2 |
Irena |
| institution |
UTIA-B |
| fullinstit |
Ústav teorie informace a automatizace AV ČR, v. v. i. |
|
| source |
|
| cas_special |
| research |
CEZ:AV0Z10750506 |
| abstract
(eng) |
We propose a simple and fast two-level minimization algorithm for completely specified functions in this paper. The algorithm is based on processing ternary trees. A ternary tree is proposed as a structure enabling a very compact representation of completely specified Boolean functions. The minimization algorithm is thus most suited for functions described by many on-set terms. When these functions are to be minimized, most of the state-of-the-art minimizers (Espresso) need prohibitively long time to process them, or they are even completely unusable, due to their very high memory consumption. Our algorithm is able to minimize such functions in a reasonable time, though the result quality does not reach the quality of other minimizers. Here our minimizer found its application as a pre-processor that, when run prior to, e.g., Espresso, significantly reduces total minimization time, while fully retaining the result quality. |
| abstract
(cze) |
Rychlá minimalizace kompletně zadaných logických funkcí pomocí binárních rozhodovacích diagramů. |
| action |
| ARLID |
cav_un_auth*0242312 |
| name |
11th IEEE Design and Diagnostics of Electronic Circuits and Systems Workshop 2008 |
| place |
Bratislava |
| dates |
16.04.2008-18.04.2008 |
| country |
SK |
|
| reportyear |
2009 |
| RIV |
BD |
| permalink |
http://hdl.handle.net/11104/0163342 |
| arlyear |
2008 |
| mrcbU34 |
000256936300025 WOS |
| mrcbU56 |
pdf |
| mrcbU63 |
cav_un_epca*0312222 Proc. of 11th IEEE Design and Diagnostics of Electronic Circuits and Systems Workshop 2008 978-1-4244-2276-0 122 127 Los Alamitos IEEE 2008 |
|