| bibtype |
C -
Conference Paper (international conference)
|
| ARLID |
0342262 |
| utime |
20240111140739.1 |
| mtime |
20100617235959.9 |
| title
(primary) (eng) |
Instruction Set Extensions for Multi-Threading in LEON3 |
| specification |
| page_count |
6 s. |
| media_type |
www |
|
| serial |
| ARLID |
cav_un_epca*0343971 |
| ISBN |
978-1-4244-6610-8 |
| title
|
Proceedings of the13th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems |
| page_num |
237-242 |
| publisher |
| place |
Los Alamitos |
| name |
IEEE |
| year |
2010 |
|
|
| keyword |
multithreading |
| keyword |
instruction set extensions |
| keyword |
microthreading |
| keyword |
LEON3 |
| keyword |
SPARC |
| keyword |
FPGA |
| author
(primary) |
| ARLID |
cav_un_auth*0101077 |
| name1 |
Daněk |
| name2 |
Martin |
| full_dept (cz) |
Zpracování signálů |
| full_dept (eng) |
Department of Signal Processing |
| department (cz) |
ZS |
| department (eng) |
ZS |
| institution |
UTIA-B |
| fullinstit |
Ústav teorie informace a automatizace AV ČR, v. v. i. |
|
| author
|
| ARLID |
cav_un_auth*0202863 |
| name1 |
Kafka |
| name2 |
Leoš |
| full_dept (cz) |
Zpracování signálů |
| full_dept |
Department of Signal Processing |
| department (cz) |
ZS |
| department |
ZS |
| institution |
UTIA-B |
| fullinstit |
Ústav teorie informace a automatizace AV ČR, v. v. i. |
|
| author
|
| ARLID |
cav_un_auth*0225749 |
| name1 |
Kohout |
| name2 |
Lukáš |
| full_dept (cz) |
Zpracování signálů |
| full_dept |
Department of Signal Processing |
| department (cz) |
ZS |
| department |
ZS |
| institution |
UTIA-B |
| full_dept |
Department of Signal Processing |
| fullinstit |
Ústav teorie informace a automatizace AV ČR, v. v. i. |
|
| author
|
| ARLID |
cav_un_auth*0261496 |
| name1 |
Sýkora |
| name2 |
Jaroslav |
| full_dept (cz) |
Zpracování signálů |
| full_dept |
Department of Signal Processing |
| department (cz) |
ZS |
| department |
ZS |
| institution |
UTIA-B |
| fullinstit |
Ústav teorie informace a automatizace AV ČR, v. v. i. |
|
| source |
|
| cas_special |
| project |
| project_id |
FP7-ICT-215216 |
| agency |
European Commission |
| country |
BE |
|
| project |
| project_id |
7E08013 |
| agency |
GA MŠk |
| ARLID |
cav_un_auth*0254219 |
|
| research |
CEZ:AV0Z10750506 |
| abstract
(eng) |
This paper describes instruction set extensions for a variant of multi-threading called micro-threading for the LEON3 SPARCv8 processor. We show an architecture of the developed processor and its key blocks - cache controller, register file, thread scheduler. The processor has been implemented in a Xilinx Virtex2Pro FPGA. The extensions are evaluated in terms of extra resources needed, and the overall performance of the developed processor is evaluated on a simple DSP computation typical for embedded systems. |
| action |
| ARLID |
cav_un_auth*0261497 |
| name |
DDECS 2010 : 13th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems |
| place |
Vídeň |
| dates |
14.04.2010-16.04.2010 |
| country |
AT |
|
| reportyear |
2011 |
| RIV |
JC |
| permalink |
http://hdl.handle.net/11104/0185041 |
| arlyear |
2010 |
| mrcbU56 |
pdf |
| mrcbU63 |
cav_un_epca*0343971 Proceedings of the13th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems 978-1-4244-6610-8 237 242 Los Alamitos IEEE 2010 |
|