| bibtype |
C -
Conference Paper (international conference)
|
| ARLID |
0342301 |
| utime |
20240111140739.1 |
| mtime |
20100423235959.9 |
| title
(primary) (eng) |
Reconfigurable Hardware Objects for Image Processing on FPGAs |
| specification |
| page_count |
2 s. |
| media_type |
www |
|
| serial |
| ARLID |
cav_un_epca*0342299 |
| ISBN |
978-1-4244-6610-8 |
| title
|
Proceedings of the 13th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems |
| page_num |
121-122 |
| publisher |
| place |
Vienna |
| name |
Institute of Electrical and Electronics Engineers |
| year |
2010 |
|
|
| keyword |
Image Processing |
| keyword |
Reconfiguration |
| keyword |
Hardware Object |
| keyword |
FPGA |
| author
(primary) |
| ARLID |
cav_un_auth*0225750 |
| name1 |
Kloub |
| name2 |
Jan |
| full_dept (cz) |
Zpracování signálů |
| full_dept (eng) |
Department of Signal Processing |
| department (cz) |
ZS |
| department (eng) |
ZS |
| institution |
UTIA-B |
| fullinstit |
Ústav teorie informace a automatizace AV ČR, v. v. i. |
|
| author
|
| ARLID |
cav_un_auth*0108102 |
| name1 |
Honzík |
| name2 |
Petr |
| full_dept (cz) |
Zpracování signálů |
| full_dept |
Department of Signal Processing |
| department (cz) |
ZS |
| department |
ZS |
| institution |
UTIA-B |
| fullinstit |
Ústav teorie informace a automatizace AV ČR, v. v. i. |
|
| author
|
| ARLID |
cav_un_auth*0101077 |
| name1 |
Daněk |
| name2 |
Martin |
| full_dept (cz) |
Zpracování signálů |
| full_dept |
Department of Signal Processing |
| department (cz) |
ZS |
| department |
ZS |
| institution |
UTIA-B |
| fullinstit |
Ústav teorie informace a automatizace AV ČR, v. v. i. |
|
| source |
|
| cas_special |
| project |
| project_id |
7H09005 |
| agency |
GA MŠk |
| ARLID |
cav_un_auth*0253180 |
|
| research |
CEZ:AV0Z10750506 |
| abstract
(eng) |
Embedded systems are getting more complex; that is why the high level of abstraction is required during the development process. High abstraction methods simplify implementation of complex computation systems and shorten the time to market. This paper presents an implementation of a graphic computing element (GCE) which can be used as a runtime parametrized building block in image processing applications in FPGAs. In terms of the object oriented model GCE encapsulates its internal data representation and rules for their manipulation. Several basic image processing operations have been implemented (Sobel edge detection, Gauss, mean, etc. filtering). These operations are called as GCE methods. Because of high spatial dependency of image data in image processing, an efficient image data reuse method has been implemented. |
| action |
| ARLID |
cav_un_auth*0261516 |
| name |
Proceedings of the 13th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems |
| place |
Vienna |
| dates |
14.04.2010-16.04.2010 |
| country |
AT |
|
| reportyear |
2011 |
| RIV |
JC |
| permalink |
http://hdl.handle.net/11104/0185067 |
| arlyear |
2010 |
| mrcbU56 |
pdf |
| mrcbU63 |
cav_un_epca*0342299 Proceedings of the 13th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems 978-1-4244-6610-8 121 122 Proceedings of the 13th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems Vienna Institute of Electrical and Electronics Engineers 2010 |
|