| bibtype |
C -
Conference Paper (international conference)
|
| ARLID |
0346745 |
| utime |
20240103193810.0 |
| mtime |
20100914235959.9 |
| title
(primary) (eng) |
Reducing Power Consumption of an Embedded DSP Platform through the Clock-Gating Technique |
| specification |
|
| serial |
| ARLID |
cav_un_epca*0347026 |
| ISBN |
978-0-7695-4179-2 |
| title
|
Proceedings of the International Conference on Field Programmable Logic and Applications |
| page_num |
336-339 |
| publisher |
| place |
Piscataway |
| name |
IEEE |
| year |
2010 |
|
|
| keyword |
FPGA |
| keyword |
Clock Gating |
| keyword |
Digital design |
| keyword |
System on Chip |
| keyword |
Multicore Embedded System |
| keyword |
Power consumption |
| author
(primary) |
| ARLID |
cav_un_auth*0101105 |
| name1 |
Heřmánek |
| name2 |
Antonín |
| full_dept (cz) |
Zpracování signálů |
| full_dept (eng) |
Department of Signal Processing |
| department (cz) |
ZS |
| department (eng) |
ZS |
| institution |
UTIA-B |
| fullinstit |
Ústav teorie informace a automatizace AV ČR, v. v. i. |
|
| author
|
| ARLID |
cav_un_auth*0218430 |
| name1 |
Kuneš |
| name2 |
Michal |
| full_dept (cz) |
Zpracování obrazové informace |
| full_dept |
Department of Image Processing |
| department (cz) |
ZOI |
| department |
ZOI |
| institution |
UTIA-B |
| full_dept |
Department of Image Processing |
| fullinstit |
Ústav teorie informace a automatizace AV ČR, v. v. i. |
|
| author
|
| ARLID |
cav_un_auth*0101213 |
| name1 |
Tichý |
| name2 |
Milan |
| full_dept (cz) |
Zpracování signálů |
| full_dept |
Department of Signal Processing |
| department (cz) |
ZS |
| department |
ZS |
| institution |
UTIA-B |
| fullinstit |
Ústav teorie informace a automatizace AV ČR, v. v. i. |
|
| source |
|
| cas_special |
| project |
| project_id |
7H09005 |
| agency |
GA MŠk |
| ARLID |
cav_un_auth*0253180 |
|
| research |
CEZ:AV0Z10750506 |
| abstract
(eng) |
The paper describes application of the clock-gating techniques, often used in ASIC designs, to the field of FPGAbased systems. The clock-gating techniques are used to reduce the total power of the system. To achieve this, we reduce clock power consumption of the system by switching-off the clock signal for the parts of system that are not used. The system presented in this paper is based on the main processor, extended with several reconfigurable accelerators. These accelerators extend the processor capabilities by several vector operations and can be reprogrammed in run-time. Clock gating, in our design, is used to switch the accelerators off when not used. As the accelerators can represent a major part of the system size, switching them off can significantly reduce the power consumption. We also propose the method for estimation of the reduction of power consumption that can be achieved using the clock-gating technique. |
| action |
| ARLID |
cav_un_auth*0263761 |
| name |
20th International Conference on Field Programmable Logic and Applications |
| place |
Milano |
| dates |
31.08.2010-02.09.2010 |
| country |
IT |
|
| reportyear |
2011 |
| RIV |
JA |
| permalink |
http://hdl.handle.net/11104/0187684 |
| arlyear |
2010 |
| mrcbU63 |
cav_un_epca*0347026 Proceedings of the International Conference on Field Programmable Logic and Applications 978-0-7695-4179-2 336 339 Piscataway IEEE 2010 |
|