| bibtype |
C -
Conference Paper (international conference)
|
| ARLID |
0357150 |
| utime |
20240103194929.2 |
| mtime |
20110307235959.9 |
| WOS |
000296828800010 |
| SCOPUS |
79952036320 |
| DOI |
10.1007/978-3-642-19137-4_10 |
| title
(primary) (eng) |
Analysis of Execution Efficiency in the Microthreaded Processor UTLEON3 |
| specification |
|
| serial |
| ARLID |
cav_un_epca*0357149 |
| ISBN |
978-3-642-19136-7 |
| ISSN |
0302-9743 |
| title
|
Architecture of Computing Systems - ARCS 2011 |
| page_num |
110-121 |
| publisher |
| place |
Berlin |
| name |
Springer-Verlag Berlin Heidelberg |
| year |
2011 |
|
| editor |
| name1 |
Berekovic |
| name2 |
Mladen |
|
|
| keyword |
Processor architectures |
| keyword |
Multi-threading |
| author
(primary) |
| ARLID |
cav_un_auth*0261496 |
| name1 |
Sýkora |
| name2 |
Jaroslav |
| full_dept (cz) |
Zpracování signálů |
| full_dept (eng) |
Department of Signal Processing |
| department (cz) |
ZS |
| department (eng) |
ZS |
| institution |
UTIA-B |
| fullinstit |
Ústav teorie informace a automatizace AV ČR, v. v. i. |
|
| author
|
| ARLID |
cav_un_auth*0202863 |
| name1 |
Kafka |
| name2 |
Leoš |
| full_dept (cz) |
Zpracování signálů |
| full_dept |
Department of Signal Processing |
| department (cz) |
ZS |
| department |
ZS |
| institution |
UTIA-B |
| fullinstit |
Ústav teorie informace a automatizace AV ČR, v. v. i. |
|
| author
|
| ARLID |
cav_un_auth*0101077 |
| name1 |
Daněk |
| name2 |
Martin |
| full_dept (cz) |
Zpracování signálů |
| full_dept |
Department of Signal Processing |
| department (cz) |
ZS |
| department |
ZS |
| institution |
UTIA-B |
| fullinstit |
Ústav teorie informace a automatizace AV ČR, v. v. i. |
|
| author
|
| ARLID |
cav_un_auth*0225749 |
| name1 |
Kohout |
| name2 |
Lukáš |
| full_dept (cz) |
Zpracování signálů |
| full_dept |
Department of Signal Processing |
| department (cz) |
ZS |
| department |
ZS |
| institution |
UTIA-B |
| full_dept |
Department of Signal Processing |
| fullinstit |
Ústav teorie informace a automatizace AV ČR, v. v. i. |
|
| cas_special |
| project |
| project_id |
7E08013 |
| agency |
GA MŠk |
| ARLID |
cav_un_auth*0254219 |
|
| project |
| project_id |
FP7-ICT-215215 |
| agency |
European Commission |
| country |
XE |
|
| research |
CEZ:AV0Z10750506 |
| abstract
(eng) |
We analyse an impact of long-latency instructions, the family blocksize parameter, and the thread switch modifier on execution efficiency of families of threads in a single-core configuration of the UTLEON3 processor that implements the SVP microthreading model. The analysis is supported by code execution in an FPGA implementation of the processor. The conclusions drawn in this paper can be used to optimize code compilation for the microthreaded processor. As the compiler specifies the blocksize parameter for each family of threads individually, it can optimize the register file utilization of the processor. |
| action |
| ARLID |
cav_un_auth*0270702 |
| name |
ARCS 2011. International Conference on Architecture of computing systems /24./ |
| place |
Camo |
| dates |
24.02.2011-25.02.2011 |
| country |
IT |
|
| reportyear |
2011 |
| RIV |
JC |
| permalink |
http://hdl.handle.net/11104/0195483 |
| mrcbT16-q |
100 |
| mrcbT16-s |
0.336 |
| mrcbT16-y |
16.35 |
| mrcbT16-x |
0.4 |
| arlyear |
2011 |
| mrcbU14 |
79952036320 SCOPUS |
| mrcbU34 |
000296828800010 WOS |
| mrcbU63 |
cav_un_epca*0357149 Architecture of Computing Systems - ARCS 2011 978-3-642-19136-7 0302-9743 110 121 Berlin Springer-Verlag Berlin Heidelberg 2011 Lecture Notes in Computer Science - LNCS 6566 |
| mrcbU67 |
Berekovic Mladen 340 |
|