bibtype C - Conference Paper (international conference)
ARLID 0373960
utime 20240103200552.4
mtime 20120312235959.9
WOS 000312912900090
DOI 10.1109/DDECS.2011.5783135
title (primary) (eng) Dynamic Placement Applications into Self Adaptive Network on FPGA
specification
page_count 4 s.
serial
ARLID cav_un_epca*0373959
ISBN 978-1-4244-9755-3
title 2011 IEEE 14th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS 2011)
page_num 453-456
publisher
place Cottbus
name Institute of Electrical and Electronics Engineers ( IEEE )
year 2011
editor
name1 Vierhaus
name2 Heinrich T.
editor
name1 Pawlak
name2 Adam
editor
name1 Schölzel
name2 Mario
editor
name1 Steininger
name2 Andreas
editor
name1 Kraemer
name2 Rolf
editor
name1 Raik
name2 Jaan
keyword FPGA
keyword reconfiguration
keyword adaptivity
keyword placement
keyword network-on-chip
author (primary)
ARLID cav_un_auth*0233557
name1 Honzík
name2 P.
country CZ
author
ARLID cav_un_auth*0101120
name1 Kadlec
name2 Jiří
full_dept (cz) Zpracování signálů
full_dept Department of Signal Processing
department (cz) ZS
department ZS
institution UTIA-B
full_dept Department of Signal Processing
fullinstit Ústav teorie informace a automatizace AV ČR, v. v. i.
source
url http://library.utia.cas.cz/separaty/2012/ZS/kadlec-dynamic placement applications into self adaptive network on fpga.pdf
cas_special
project
project_id 7H10001
agency GA MŠk
country CZ
ARLID cav_un_auth*0272880
research CEZ:AV0Z10750506
abstract (eng) The presented work deals with reconfigurable systems with Self Adaptivity based on the FPGA technology. The work is based on partial dynamic reconfiguration of FPGA devices and analyzes Self Adaptive systems, their elements and features. The main part introduces placement algorithms and Step Adaptive algorithm for improving mapping on running network. The tests of algorithm are done on the sets of the test applications.
action
ARLID cav_un_auth*0279452
name 14th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS 2011)
place Cottbus
dates 13.04.2011-15.04.2011
country DE
reportyear 2012
RIV JC
num_of_auth 2
presentation_type PR
permalink http://hdl.handle.net/11104/0206994
arlyear 2011
mrcbU34 000312912900090 WOS
mrcbU63 cav_un_epca*0373959 2011 IEEE 14th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS 2011) 978-1-4244-9755-3 453 456 Cottbus Institute of Electrical and Electronics Engineers ( IEEE ) 2011 CFP11DDE-PRT
mrcbU67 Vierhaus Heinrich T. 340
mrcbU67 Pawlak Adam 340
mrcbU67 Schölzel Mario 340
mrcbU67 Steininger Andreas 340
mrcbU67 Kraemer Rolf 340
mrcbU67 Raik Jaan 340