| bibtype |
C -
Conference Paper (international conference)
|
| ARLID |
0380442 |
| utime |
20240103201204.9 |
| mtime |
20121031235959.9 |
| title
(primary) (eng) |
Reducing Instruction Issue Overheads in Application-Specific Vector Processors |
| specification |
| page_count |
8 s. |
| media_type |
C |
|
| serial |
| ARLID |
cav_un_epca*0380441 |
| ISBN |
978-0-7695-4798-5 |
| title
|
Proceedings of the 15th Euromicro Conference on Digital System Design, DSD 2012 |
| page_num |
600-607 |
| publisher |
| place |
Izmir |
| name |
Conference Publishing Services |
| year |
2012 |
|
| editor |
|
|
| keyword |
custom accelerators |
| keyword |
vector processing |
| keyword |
FPGA |
| keyword |
DSP |
| author
(primary) |
| ARLID |
cav_un_auth*0261496 |
| name1 |
Sýkora |
| name2 |
Jaroslav |
| full_dept (cz) |
Zpracování signálů |
| full_dept (eng) |
Department of Signal Processing |
| department (cz) |
ZS |
| department (eng) |
ZS |
| institution |
UTIA-B |
| garant |
G |
| fullinstit |
Ústav teorie informace a automatizace AV ČR, v. v. i. |
|
| author
|
| ARLID |
cav_un_auth*0202591 |
| name1 |
Bartosinski |
| name2 |
Roman |
| full_dept (cz) |
Zpracování signálů |
| full_dept |
Department of Signal Processing |
| department (cz) |
ZS |
| department |
ZS |
| institution |
UTIA-B |
| fullinstit |
Ústav teorie informace a automatizace AV ČR, v. v. i. |
|
| author
|
| ARLID |
cav_un_auth*0225749 |
| name1 |
Kohout |
| name2 |
Lukáš |
| full_dept (cz) |
Zpracování signálů |
| full_dept |
Department of Signal Processing |
| department (cz) |
ZS |
| department |
ZS |
| institution |
UTIA-B |
| full_dept |
Department of Signal Processing |
| fullinstit |
Ústav teorie informace a automatizace AV ČR, v. v. i. |
|
| author
|
| ARLID |
cav_un_auth*0101077 |
| name1 |
Daněk |
| name2 |
Martin |
| full_dept (cz) |
Zpracování signálů |
| full_dept |
Department of Signal Processing |
| department (cz) |
ZS |
| department |
ZS |
| institution |
UTIA-B |
| fullinstit |
Ústav teorie informace a automatizace AV ČR, v. v. i. |
|
| author
|
| ARLID |
cav_un_auth*0233557 |
| name1 |
Honzík |
| name2 |
P. |
| country |
CZ |
|
| source |
|
| cas_special |
| project |
| project_id |
7H10001 |
| agency |
GA MŠk |
| country |
CZ |
| ARLID |
cav_un_auth*0272880 |
|
| project |
| project_id |
Artemis JU 100230 |
| agency |
Commission EU |
| country |
XE |
| ARLID |
cav_un_auth*0283284 |
|
| abstract
(eng) |
The traditional approach to IP core design is to use simulations with test vectors. This is not feasible when dealing with complex function cores such as the Image Segmentation case-study algorithm in this paper. An algorithm developer needs to carry out experiments on large real-world data sets, with fast turn-around times, and in real time to facilitate performance tuning and incremental development. Previously we proposed a methodology called Application-Specific Vector Processor (ASVP). The ASVP approach first constructs a programmable architecture customized for a given application, then employs software techniques to develop firmware that implements the algorithm. In our setting we employ an embedded simple scalar CPU (8-bit PicoBlaze 3) to control a floating-point vector processing unit (VPU) by issuing wide (horizontally encoded) instructions to it. In this work we dramatically reduce the overhead of the wide-instruction issue (in one case by 13x) by implementing a new two-level configuration table. |
| action |
| ARLID |
cav_un_auth*0283283 |
| name |
15th Euromicro Conference on Digital System Design |
| place |
Cesme |
| dates |
05.09.2012-08.09.2012 |
| country |
TR |
|
| reportyear |
2013 |
| RIV |
JC |
| num_of_auth |
5 |
| presentation_type |
PR |
| permalink |
http://hdl.handle.net/11104/0211153 |
| arlyear |
2012 |
| mrcbU63 |
cav_un_epca*0380441 Proceedings of the 15th Euromicro Conference on Digital System Design, DSD 2012 978-0-7695-4798-5 600 607 Izmir Conference Publishing Services 2012 |
| mrcbU67 |
Niar Smail 340 |
|