| bibtype |
J -
Journal Article
|
| ARLID |
0380861 |
| utime |
20240103201233.0 |
| mtime |
20121011235959.9 |
| title
(primary) (eng) |
Hardware Support for Fine-Grain Multi-Threading in LEON3 |
| specification |
|
| serial |
| ARLID |
cav_un_epca*0380860 |
| ISSN |
1844-9689 |
| title
|
Carpathian Journal of Electronic and Computer Engineering |
| part_title |
Carpathian Journal of Electronic and Computer Engineering |
| volume_id |
4 |
| volume |
1 (2011) |
| page_num |
27-34 |
|
| keyword |
multithreading |
| keyword |
microthreading |
| keyword |
SPARC |
| keyword |
microarchitecture |
| keyword |
FPGA |
| author
(primary) |
| ARLID |
cav_un_auth*0101077 |
| name1 |
Daněk |
| name2 |
Martin |
| full_dept (cz) |
Zpracování signálů |
| full_dept (eng) |
Department of Signal Processing |
| department (cz) |
ZS |
| department (eng) |
ZS |
| institution |
UTIA-B |
| fullinstit |
Ústav teorie informace a automatizace AV ČR, v. v. i. |
|
| author
|
| ARLID |
cav_un_auth*0202863 |
| name1 |
Kafka |
| name2 |
Leoš |
| full_dept (cz) |
Zpracování signálů |
| full_dept |
Department of Signal Processing |
| department (cz) |
ZS |
| department |
ZS |
| institution |
UTIA-B |
| fullinstit |
Ústav teorie informace a automatizace AV ČR, v. v. i. |
|
| author
|
| ARLID |
cav_un_auth*0225749 |
| name1 |
Kohout |
| name2 |
Lukáš |
| full_dept (cz) |
Zpracování signálů |
| full_dept |
Department of Signal Processing |
| department (cz) |
ZS |
| department |
ZS |
| institution |
UTIA-B |
| full_dept |
Department of Signal Processing |
| fullinstit |
Ústav teorie informace a automatizace AV ČR, v. v. i. |
|
| author
|
| ARLID |
cav_un_auth*0261496 |
| name1 |
Sýkora |
| name2 |
Jaroslav |
| full_dept (cz) |
Zpracování signálů |
| full_dept |
Department of Signal Processing |
| department (cz) |
ZS |
| department |
ZS |
| institution |
UTIA-B |
| fullinstit |
Ústav teorie informace a automatizace AV ČR, v. v. i. |
|
| source |
|
| cas_special |
| project |
| project_id |
7E08013 |
| agency |
GA MŠk |
| ARLID |
cav_un_auth*0254219 |
|
| project |
| project_id |
FP7-ICT-215216 |
| agency |
European Commission |
| country |
BE |
|
| abstract
(eng) |
The article describes instruction set extensions for a variant of multi-threading called micro-threading for the LEON3 SPARCv8 processor. An architecture of the developed processor is presented and its key blocks described - cache controller, register file, thread scheduler. The processor has been implemented in a Xilinx Virtex2Pro and Virtex5 FPGAs. The extensions are evaluated in terms of extra resources needed, and the overall performance of the developed processor is shown for a simple DSP computation typical for embedded systems. |
| reportyear |
2013 |
| RIV |
JC |
| num_of_auth |
4 |
| mrcbC52 |
4 A 4a 20231122135212.8 |
| permalink |
http://hdl.handle.net/11104/0211467 |
| arlyear |
2011 |
| mrcbTft |
\nSoubory v repozitáři: danek-0380861.pdf |
| mrcbU63 |
cav_un_epca*0380860 Carpathian Journal of Electronic and Computer Engineering Carpathian Journal of Electronic and Computer Engineering 1844-9689 Roč. 4 č. 1 2011 27 34 |
|