bibtype B - Monography
ARLID 0380863
utime 20240103201233.2
mtime 20121119235959.9
ISBN 978-1-4614-2409-3
DOI 10.1007/978-1-4614-2410-9
title (primary) (eng) UTLEON3: Exploring Fine-Grain Multi-Threading in FPGAs
publisher
place New York
name Springer
pub_time 2013
specification
page_count 209 s.
media_type P
edition
name Circuits & Systems
keyword multi-threading
keyword micro-threading
keyword SPARC
keyword LEON3
keyword hardware acceleration
keyword FPGA
keyword GRLIB
author (primary)
ARLID cav_un_auth*0101077
name1 Daněk
name2 Martin
full_dept (cz) Zpracování signálů
full_dept (eng) Department of Signal Processing
department (cz) ZS
department (eng) ZS
institution UTIA-B
fullinstit Ústav teorie informace a automatizace AV ČR, v. v. i.
author
ARLID cav_un_auth*0202863
name1 Kafka
name2 Leoš
full_dept (cz) Zpracování signálů
full_dept Department of Signal Processing
department (cz) ZS
department ZS
institution UTIA-B
fullinstit Ústav teorie informace a automatizace AV ČR, v. v. i.
author
ARLID cav_un_auth*0225749
name1 Kohout
name2 Lukáš
full_dept (cz) Zpracování signálů
full_dept Department of Signal Processing
department (cz) ZS
department ZS
institution UTIA-B
full_dept Department of Signal Processing
fullinstit Ústav teorie informace a automatizace AV ČR, v. v. i.
author
ARLID cav_un_auth*0261496
name1 Sýkora
name2 Jaroslav
full_dept (cz) Zpracování signálů
full_dept Department of Signal Processing
department (cz) ZS
department ZS
institution UTIA-B
fullinstit Ústav teorie informace a automatizace AV ČR, v. v. i.
author
ARLID cav_un_auth*0202591
name1 Bartosinski
name2 Roman
full_dept (cz) Zpracování signálů
full_dept Department of Signal Processing
department (cz) ZS
department ZS
institution UTIA-B
fullinstit Ústav teorie informace a automatizace AV ČR, v. v. i.
cas_special
project
project_id 7E08013
agency GA MŠk
ARLID cav_un_auth*0254219
project
project_id FP7-ICT-215216
agency European Commission
country BE
abstract (eng) This book describes a specification, microarchitecture, VHDL implementation and evaluation of a SPARC v8 CPU with fine-grain multi-threading, called micro-threading. The CPU, named UTLEON3, is an alternative platform for exploring CPU multi-threading that is compatible with the industry-standard GRLIB package. The processor microarchitecture was designed to map in an efficient way the data-flow scheme on a classical von Neumann pipelined processing used in common processors, while retaining full binary compatibility with existing legacy programs. * Describes and documents a working SPARC v8, with fine-grain multithreading and fast context switch; * Provides VHDL sources for the described processor; * Describes a latency-tolerant framework for coupling hardware accelerators to microthreaded processor pipelines; * Includes programming by example in the micro-threaded assembly language.
reportyear 2013
RIV JC
num_of_auth 5
mrcbC52 4 A 4a 20231122135213.0
permalink http://hdl.handle.net/11104/0211468
arlyear 2013
mrcbTft \nSoubory v repozitáři: danek-0380863.pdf
mrcbU10 2013
mrcbU10 New York Springer
mrcbU12 978-1-4614-2409-3