bibtype |
C -
Conference Paper (international conference)
|
ARLID |
0382187 |
utime |
20240103201405.3 |
mtime |
20121105235959.9 |
title
(primary) (eng) |
Foreground Detection and Image Segmentation in a Flexible ASVP Platform for FPGAs |
specification |
page_count |
2 s. |
media_type |
C |
|
serial |
ARLID |
cav_un_epca*0382183 |
ISBN |
978-2-9539987-2-6 |
ISSN |
1966-7116 |
title
|
Proceedings of the 2012 Conference on Design & Architectures for Signal & Image Processing |
page_num |
375-376 |
publisher |
place |
Gières |
name |
Electronic Chips & Systems design Initiative |
year |
2012 |
|
editor |
name1 |
Morawiec |
name2 |
Adam |
|
editor |
name1 |
Hinderscheit |
name2 |
Jinnie |
|
|
keyword |
video surveillance |
keyword |
smart camera |
keyword |
custom accelerators |
keyword |
vector processing |
keyword |
FPGA |
author
(primary) |
ARLID |
cav_un_auth*0202591 |
name1 |
Bartosinski |
name2 |
Roman |
full_dept (cz) |
Zpracování signálů |
full_dept (eng) |
Department of Signal Processing |
department (cz) |
ZS |
department (eng) |
ZS |
institution |
UTIA-B |
fullinstit |
Ústav teorie informace a automatizace AV ČR, v. v. i. |
|
author
|
ARLID |
cav_un_auth*0101077 |
name1 |
Daněk |
name2 |
Martin |
full_dept (cz) |
Zpracování signálů |
full_dept |
Department of Signal Processing |
department (cz) |
ZS |
department |
ZS |
institution |
UTIA-B |
fullinstit |
Ústav teorie informace a automatizace AV ČR, v. v. i. |
|
author
|
ARLID |
cav_un_auth*0261496 |
name1 |
Sýkora |
name2 |
Jaroslav |
full_dept (cz) |
Zpracování signálů |
full_dept |
Department of Signal Processing |
department (cz) |
ZS |
department |
ZS |
institution |
UTIA-B |
fullinstit |
Ústav teorie informace a automatizace AV ČR, v. v. i. |
|
author
|
ARLID |
cav_un_auth*0225749 |
name1 |
Kohout |
name2 |
Lukáš |
full_dept (cz) |
Zpracování signálů |
full_dept |
Department of Signal Processing |
department (cz) |
ZS |
department |
ZS |
institution |
UTIA-B |
full_dept |
Department of Signal Processing |
fullinstit |
Ústav teorie informace a automatizace AV ČR, v. v. i. |
|
author
|
ARLID |
cav_un_auth*0233557 |
name1 |
Honzík |
name2 |
P. |
country |
CZ |
|
source |
|
cas_special |
project |
project_id |
7H10001 |
agency |
GA MŠk |
country |
CZ |
ARLID |
cav_un_auth*0272880 |
|
abstract
(eng) |
This demonstration shows an early prototype of low-level image processing to be used in an embedded smart camera, that is foreground detection and image segmentation. The example uses camera with resolution 640x480 pixels for input images processed at 100MHz in the FPGA. The input can be easily extended to higher resolutions. The processed output is displayed on LCD screen. |
action |
ARLID |
cav_un_auth*0284632 |
name |
Conference on Design & Architectures for Signal & Image Processing |
place |
Karlsruhe |
dates |
23.10.2012-25.10.2012 |
country |
DE |
|
reportyear |
2013 |
RIV |
JC |
presentation_type |
PO |
inst_support |
RVO:67985556 |
permalink |
http://hdl.handle.net/11104/0212481 |
arlyear |
2012 |
mrcbU63 |
cav_un_epca*0382183 Proceedings of the 2012 Conference on Design & Architectures for Signal & Image Processing 978-2-9539987-2-6 1966-7116 375 376 Gières Electronic Chips & Systems design Initiative 2012 |
mrcbU67 |
Morawiec Adam 340 |
mrcbU67 |
Hinderscheit Jinnie 340 |
|