| bibtype |
L -
Prototype, methodology, f. module, software
|
| ARLID |
0384519 |
| utime |
20240103201637.5 |
| mtime |
20121210235959.9 |
| title
(primary) (cze) |
DMA jednotka pro BCE v systémech s AXI sběrnicí |
| publisher |
|
| title
(eng) |
BCE DMA unit for designs with AXI bus |
| keyword |
AXI |
| keyword |
DMA |
| keyword |
BCE |
| keyword |
worker |
| keyword |
FPGA |
| keyword |
Xilinx |
| author
(primary) |
| ARLID |
cav_un_auth*0101179 |
| name1 |
Pohl |
| name2 |
Zdeněk |
| full_dept (cz) |
Zpracování signálů |
| full_dept (eng) |
Department of Signal Processing |
| department (cz) |
ZS |
| department (eng) |
ZS |
| institution |
UTIA-B |
| full_dept |
Department of Signal Processing |
| fullinstit |
Ústav teorie informace a automatizace AV ČR, v. v. i. |
|
| source |
|
| cas_special |
| project |
| project_id |
7H10001 |
| agency |
GA MŠk |
| country |
CZ |
| ARLID |
cav_un_auth*0272880 |
|
| abstract
(cze) |
Hardwarovy modul zajistujici komunikaci pro BCE wokery v FPGA projektech s AXI sbernici. |
| abstract
(eng) |
Hardware IP core providing DMA functionality to the BCE workers in FPGA designs with AXI bus. |
| reportyear |
2013 |
| RIV |
IN |
| inst_support |
RVO:67985556 |
| permalink |
http://hdl.handle.net/11104/0214142 |
| arlyear |
2012 |
| mrcbU10 |
2012 |
|