| bibtype |
A -
Abstract
|
| ARLID |
0391650 |
| utime |
20240103202452.4 |
| mtime |
20130502235959.9 |
| title
(primary) (eng) |
EDKDSP: Reprogrammable Floating Point Accelerators on KINTEX FPGA with HDMI |
| specification |
| page_count |
1 s. |
| media_type |
E |
|
| serial |
| ARLID |
cav_un_epca*0391649 |
| title
|
2013 Design, Automation and Test in Europe |
| publisher |
|
|
| keyword |
FPGA |
| keyword |
programmable accelerators |
| keyword |
computer video processing |
| author
(primary) |
| ARLID |
cav_un_auth*0101120 |
| name1 |
Kadlec |
| name2 |
Jiří |
| full_dept (cz) |
Zpracování signálů |
| full_dept (eng) |
Department of Signal Processing |
| department (cz) |
ZS |
| department (eng) |
ZS |
| institution |
UTIA-B |
| full_dept |
Department of Signal Processing |
| fullinstit |
Ústav teorie informace a automatizace AV ČR, v. v. i. |
|
| source |
|
| cas_special |
| project |
| project_id |
7H12004 |
| agency |
GA MŠk |
| country |
CZ |
| ARLID |
cav_un_auth*0290082 |
|
| abstract
(eng) |
Presentation of the EdkDSP reprogrammable floating point accelerators on the Xilinx Kintex FPGA (KC705) together with the HDMI video I/O (ON Semiconductor Image sensor/HDMI 1080p60). Presented SoC is using the 512 bit wide AXI-4 buses and several independent VDMA controllers. |
| action |
| ARLID |
cav_un_auth*0290577 |
| name |
DATE 2013 Design, Automation and Test in Europe |
| place |
Grenoble |
| dates |
2013.03.18-2013.03.22 |
| country |
FR |
|
| reportyear |
2014 |
| RIV |
JC |
| num_of_auth |
1 |
| mrcbC52 |
4 O 4o 20231122135603.4 |
| presentation_type |
PO |
| permalink |
http://hdl.handle.net/11104/0221083 |
| mrcbC61 |
1 |
| arlyear |
2013 |
| mrcbTft |
\nSoubory v repozitáři: 0391650.pdf |
| mrcbU63 |
cav_un_epca*0391649 2013 Design, Automation and Test in Europe Grenoble 2013 |
|