| bibtype |
C -
Conference Paper (international conference)
|
| ARLID |
0409183 |
| utime |
20240103182052.5 |
| mtime |
20060210235959.9 |
| ISBN |
0-4448-2106-6 |
| title
(primary) (eng) |
A systolic algorithm for block-regularized RLS identification |
| publisher |
| place |
Amsterdam |
| name |
Elsevier |
| pub_time |
1994 |
|
| serial |
| title
|
Algorithms and Parallel VLSI Architectures III |
| page_num |
49-60 |
| editor |
|
| editor |
|
|
| author
(primary) |
| ARLID |
cav_un_auth*0101190 |
| name1 |
Schier |
| name2 |
Jan |
| institution |
UTIA-B |
| full_dept |
Department of Image Processing |
| fullinstit |
Ústav teorie informace a automatizace AV ČR, v. v. i. |
|
| COSATI |
09I |
| cas_special |
| project |
| project_id |
102/93/0897 |
| agency |
GA ČR |
| ARLID |
cav_un_auth*0211931 |
|
| action |
| ARLID |
cav_un_auth*0212100 |
| name |
Algorithms and Parallel VLSI Architectures /3./ |
| place |
Leuven |
| country |
BE |
| dates |
29.08.1994-31.08.1994 |
|
| department |
AS |
| permalink |
http://hdl.handle.net/11104/0129284 |
| ID_orig |
UTIA-B 950179 |
| arlyear |
1994 |
| mrcbU10 |
1994 |
| mrcbU10 |
Amsterdam Elsevier |
| mrcbU12 |
0-4448-2106-6 |
| mrcbU63 |
Algorithms and Parallel VLSI Architectures III 49 60 |
| mrcbU67 |
Moonen M. 340 |
| mrcbU67 |
Catthor F. 340 |
|