bibtype	C - Conference Paper (international conference)
ARLID	0410645
utime	20240103182228.8
mtime	20060210235959.9
title (primary) (eng)	FPGA implementation of logarithmic unit core
publisher	place Nürnberg name Design & Elektronik pub_time 2001
specification	page_count 8 s.
serial	title Embedded Intelligence 2001 page_num 547-554
keyword	field programmable gate array
author (primary)	ARLID cav_un_auth*0101120 name1 Kadlec name2 Jiří institution UTIA-B full_dept Department of Signal Processing fullinstit Ústav teorie informace a automatizace AV ČR, v. v. i.
author	ARLID cav_un_auth*0101159 name1 Matoušek name2 Rudolf institution UTIA-B fullinstit Ústav teorie informace a automatizace AV ČR, v. v. i.
author	ARLID cav_un_auth*0101152 name1 Líčko name2 Miroslav institution UTIA-B fullinstit Ústav teorie informace a automatizace AV ČR, v. v. i.
COSATI	09G
COSATI	09J
cas_special	project project_id HSLA 33544 agency ESPRIT country XE project project_id 212 HSLA agency Commission EC country XE research AV0Z1075907 abstract (eng) Implementation of floatig point in FPGA (Field Programmable Gate Arrays) is not easy. Paper presents FPGA core which implements these operations by representation of floating point numbers as 32-bit integer (fixed point) logarithm. Basic arithmetical operations are performed in the logarithm numbering system (LNS) suitable for FPGA. First, we describe Matlab library emulating bit-exactly the properties of the final hardware. action ARLID cav_un_auth*0212816 name Embedded Intelligence 2001 place Nürnberg country DE dates 14.02.2001-16.02.2001 RIV JC department ZS permalink http://hdl.handle.net/11104/0130733 ID_orig UTIA-B 20010114 arlyear 2001 mrcbU10 2001 mrcbU10 Nürnberg Design & Elektronik mrcbU63 Embedded Intelligence 2001 547 554