bibtype C - Conference Paper (international conference)
ARLID 0410655
utime 20240103182229.4
mtime 20060210235959.9
ISBN 960-8052-39-4
title (primary) (eng) Implementation of Error-Feedback RLS Lattice on Virtex using logarithmic arithmetic
publisher
place Rethymno
name WSES Press
pub_time 2001
specification
page_count 5 s.
serial
title Advances in Systems Science: Measurement, Circuits and Control. Proceedings
page_num 517-521
editor
name1 Mastorakis
name2 N. E.
editor
name1 Pecorelli-Peres
name2 L. A.
keyword RLS Lattice
keyword logarithmic number system
author (primary)
ARLID cav_un_auth*0212813
name1 Albu
name2 F.
country IE
author
ARLID cav_un_auth*0101120
name1 Kadlec
name2 Jiří
institution UTIA-B
full_dept Department of Signal Processing
fullinstit Ústav teorie informace a automatizace AV ČR, v. v. i.
author
ARLID cav_un_auth*0212814
name1 Fagan
name2 A.
country IE
author
ARLID cav_un_auth*0212571
name1 Coleman
name2 J. N.
country GB
COSATI 09G
cas_special
project
project_id HSLA 33544
agency ESPRIT
country XE
research AV0Z1075907
abstract (eng) The LNS implementation of the Error-Feedback RLS Lattice algorithm in FPGA offers better speed than C30/C40 DSP floating-point and provides low- cost, efficient solution for different system on chip applications. We have demonstrated, that one can manage without a dedicated DSP processor.
action
ARLID cav_un_auth*0212774
name WSES International Conference on Circuits, Systems, Communications and Computers. CSCC 2001 /5./
place Rethymno
country GR
dates 08.07.2001-15.07.2001
RIV JC
department ZS
permalink http://hdl.handle.net/11104/0130743
ID_orig UTIA-B 20010124
arlyear 2001
mrcbU10 2001
mrcbU10 Rethymno WSES Press
mrcbU12 960-8052-39-4
mrcbU63 Advances in Systems Science: Measurement, Circuits and Control. Proceedings 517 521
mrcbU67 Mastorakis N. E. 340
mrcbU67 Pecorelli-Peres L. A. 340