| bibtype |
V -
Research Report
|
| ARLID |
0410660 |
| utime |
20240103182229.8 |
| mtime |
20060210235959.9 |
| title
(primary) (eng) |
FPGA Implementation of Logarithmic Unit Core |
| publisher |
| place |
Praha |
| name |
ÚTIA AV ČR |
| pub_time |
2001 |
|
| specification |
|
| edition |
| name |
Research Report |
| volume_id |
2007 |
|
| author
(primary) |
| ARLID |
cav_un_auth*0101120 |
| name1 |
Kadlec |
| name2 |
Jiří |
| institution |
UTIA-B |
| full_dept |
Department of Signal Processing |
| fullinstit |
Ústav teorie informace a automatizace AV ČR, v. v. i. |
|
| author
|
| ARLID |
cav_un_auth*0101159 |
| name1 |
Matoušek |
| name2 |
Rudolf |
| institution |
UTIA-B |
| fullinstit |
Ústav teorie informace a automatizace AV ČR, v. v. i. |
|
| author
|
| ARLID |
cav_un_auth*0101152 |
| name1 |
Líčko |
| name2 |
Miroslav |
| institution |
UTIA-B |
| fullinstit |
Ústav teorie informace a automatizace AV ČR, v. v. i. |
|
| COSATI |
09G |
| COSATI |
09J |
| cas_special |
| project |
| project_id |
HSLA 33544 |
| agency |
ESPRIT |
| country |
XE |
|
| research |
AV0Z1075907 |
| RIV |
JC |
| department |
ZS |
| permalink |
http://hdl.handle.net/11104/0130748 |
| ID_orig |
UTIA-B 20010129 |
| arlyear |
2001 |
| mrcbU10 |
2001 |
| mrcbU10 |
Praha ÚTIA AV ČR |
|