bibtype K - Conference Paper (Czech conference)
ARLID 0410672
utime 20240103182230.7
mtime 20060210235959.9
ISBN 80-7080-446-7
title (primary) (eng) Tuning and implementation of DSP algorithms on FPGA
publisher
place Praha
name VŠCHT
pub_time 2001
specification
page_count 5 s.
serial
title Sborník příspěvků 9.ročníku konference MATLAB 2001
page_num 226-230
editor
name1 Procházka
name2 A.
editor
name1 Uhlíř
name2 J.
author (primary)
ARLID cav_un_auth*0101152
name1 Líčko
name2 Miroslav
institution UTIA-B
fullinstit Ústav teorie informace a automatizace AV ČR, v. v. i.
author
ARLID cav_un_auth*0101179
name1 Pohl
name2 Zdeněk
institution UTIA-B
full_dept Department of Signal Processing
fullinstit Ústav teorie informace a automatizace AV ČR, v. v. i.
author
ARLID cav_un_auth*0101159
name1 Matoušek
name2 Rudolf
institution UTIA-B
fullinstit Ústav teorie informace a automatizace AV ČR, v. v. i.
author
ARLID cav_un_auth*0101105
name1 Heřmánek
name2 Antonín
institution UTIA-B
fullinstit Ústav teorie informace a automatizace AV ČR, v. v. i.
COSATI 09G
cas_special
project
project_id HSLA 33544
agency ESPRIT
country XE
research AV0Z1075907
abstract (eng) The article describes an algoritms development process for FPGA. It is shown on the example of the implementation of the QR RLS algorithm. To realise it means to perform operations such multiplication, division and square root.The research indicates, that the logarithmic arithemtic unit can reused for the real data type processing in some cases such a QR RLS algoritm.The developed prototype of logaritmic unit is tested on DSP algorithms using Matlab.
action
ARLID cav_un_auth*0212830
name MATLAB 2001 /9./
place Praha
country CZ
dates 11.10.2001
RIV JC
department ZS
permalink http://hdl.handle.net/11104/0130760
ID_orig UTIA-B 20010141
arlyear 2001
mrcbU10 2001
mrcbU10 Praha VŠCHT
mrcbU12 80-7080-446-7
mrcbU63 Sborník příspěvků 9.ročníku konference MATLAB 2001 226 230
mrcbU67 Procházka A. 340
mrcbU67 Uhlíř J. 340