bibtype C - Conference Paper (international conference)
ARLID 0410794
utime 20240103182239.7
mtime 20060210235959.9
ISBN 0-7695-1471-5
title (primary) (eng) Logarithmic arithmetic core based RLS LATTICE implementation
part_num 2
part_title Designers Forum.
publisher
place Los Alamitos
name IEEE
pub_time 2002
specification
page_count 1 s.
serial
title Design, Automation and Test in Europe DATE 02
page_num 271
editor
name1 Sciuto
name2 D.
editor
name1 Kloos
name2 C. D.
keyword logaritmic arithmetic core
keyword FPGA
keyword LNS
author (primary)
ARLID cav_un_auth*0212890
name1 Matoušek
name2 R.
country CZ
author
ARLID cav_un_auth*0212891
name1 Pohl
name2 Z.
country CZ
author
ARLID cav_un_auth*0101120
name1 Kadlec
name2 Jiří
institution UTIA-B
full_dept Department of Signal Processing
fullinstit Ústav teorie informace a automatizace AV ČR, v. v. i.
author
ARLID cav_un_auth*0101213
name1 Tichý
name2 Milan
institution UTIA-B
fullinstit Ústav teorie informace a automatizace AV ČR, v. v. i.
author
ARLID cav_un_auth*0101105
name1 Heřmánek
name2 Antonín
institution UTIA-B
fullinstit Ústav teorie informace a automatizace AV ČR, v. v. i.
COSATI 09G
COSATI 09H
cas_special
project
project_id LN00B096
agency GA MŠk
ARLID cav_un_auth*0027922
research CEZ:AV0Z1075907
abstract (eng) Presentation of HW implementation of a complete Recursive Least Square (RLS) LATTICE core for Virtex XCV800 device. The computational parallelism and ease of pipelining of LATTICE leads to easy mapping on FPGA. Demonstration of the active noise cancellation with four 20-bit parallel Logarithic Arithemtic ALUs on the XESS HW with Virtex XCV800-4.
action
ARLID cav_un_auth*0212892
name Design, Automation and Test in Europe DATE 02
place Paris
country FR
dates 04.03.2002-08.03.2002
RIV JC
department ZS
permalink http://hdl.handle.net/11104/0130881
ID_orig UTIA-B 20020008
arlyear 2002
mrcbU10 2002
mrcbU10 Los Alamitos IEEE
mrcbU12 0-7695-1471-5
mrcbU63 Design, Automation and Test in Europe DATE 02 271
mrcbU67 Sciuto D. 340
mrcbU67 Kloos C. D. 340