| bibtype |
C -
Conference Paper (international conference)
|
| ARLID |
0410795 |
| utime |
20240103182239.8 |
| mtime |
20060210235959.9 |
| ISBN |
0-7695-1471-5 |
| title
(primary) (eng) |
Matlab Toolbox for high-level bit-exact emulation of HandelC VHDL FPGA designs |
| part_num |
2 |
| part_title |
Designers˙Forum. |
| publisher |
| place |
Los Alamitos |
| name |
IEEE |
| pub_time |
2002 |
|
| specification |
|
| serial |
| title
|
Design, Automation and Test in Europe DATE˙02 |
| page_num |
264 |
| editor |
|
| editor |
|
|
| keyword |
logarithmic arithmetic |
| keyword |
matlab toolbox |
| keyword |
FPGA cores |
| author
(primary) |
| ARLID |
cav_un_auth*0101120 |
| name1 |
Kadlec |
| name2 |
Jiří |
| institution |
UTIA-B |
| full_dept |
Department of Signal Processing |
| fullinstit |
Ústav teorie informace a automatizace AV ČR, v. v. i. |
|
| author
|
| ARLID |
cav_un_auth*0101213 |
| name1 |
Tichý |
| name2 |
Milan |
| institution |
UTIA-B |
| fullinstit |
Ústav teorie informace a automatizace AV ČR, v. v. i. |
|
| author
|
| ARLID |
cav_un_auth*0101105 |
| name1 |
Heřmánek |
| name2 |
Antonín |
| institution |
UTIA-B |
| fullinstit |
Ústav teorie informace a automatizace AV ČR, v. v. i. |
|
| author
|
| ARLID |
cav_un_auth*0212891 |
| name1 |
Pohl |
| name2 |
Z. |
| country |
CZ |
|
| author
|
| ARLID |
cav_un_auth*0212893 |
| name1 |
Líčko |
| name2 |
M. |
| country |
CZ |
|
| COSATI |
09G |
| COSATI |
09H |
| cas_special |
| project |
| project_id |
LN00B096 |
| agency |
GA MŠk |
| ARLID |
cav_un_auth*0027922 |
|
| project |
| project_id |
33544 |
| agency |
ESPRIT |
| country |
XE |
|
| research |
CEZ:AV0Z1075907 |
| abstract
(eng) |
The university booth presents Matlab tolbox, which supports two possible solutions for floating-point-like ALUs, based on a 32-bit and 20-bit logarithmic arithmetic. Both Virtex FPGA cores are encapsulated in function-like API interface compatible with DK1 tool from Celoxica (Handel C).DSP designers can create optimized VLIW program flow with 32-bit or 20-bit FP-like data range and precision. Code can be source-code-debugged and compiled from high-level to the target Virtex FPGA. |
| action |
| ARLID |
cav_un_auth*0212894 |
| name |
Design, Automation and Test in Europe DATE˙02 |
| place |
Paris |
| country |
FR |
| dates |
04.03.2002-08.03.2002 |
|
| RIV |
JC |
| department |
ZS |
| permalink |
http://hdl.handle.net/11104/0130882 |
| ID_orig |
UTIA-B 20020009 |
| arlyear |
2002 |
| mrcbU10 |
2002 |
| mrcbU10 |
Los Alamitos IEEE |
| mrcbU12 |
0-7695-1471-5 |
| mrcbU63 |
Design, Automation and Test in Europe DATE˙02 264 |
| mrcbU67 |
Sciuto D. 340 |
| mrcbU67 |
Kloos C. D. 340 |
|