bibtype	C - Conference Paper (international conference)
ARLID	0410866
utime	20240103182244.8
mtime	20060210235959.9
title (primary) (eng)	Prototyping of DSP algorithms on FPGA
publisher	place Praha name FEL ČVUT pub_time 2002
specification	page_count 1 s.
serial	title POSTER 2002 page_num 2
keyword	DSP
keyword	FPGA
keyword	floating-point
author (primary)	ARLID cav_un_auth*0101152 name1 Líčko name2 Miroslav institution UTIA-B fullinstit Ústav teorie informace a automatizace AV ČR, v. v. i.
author	ARLID cav_un_auth*0101213 name1 Tichý name2 Milan institution UTIA-B fullinstit Ústav teorie informace a automatizace AV ČR, v. v. i.
author	ARLID cav_un_auth*0101105 name1 Heřmánek name2 Antonín institution UTIA-B fullinstit Ústav teorie informace a automatizace AV ČR, v. v. i.
author	ARLID cav_un_auth*0101159 name1 Matoušek name2 Rudolf institution UTIA-B fullinstit Ústav teorie informace a automatizace AV ČR, v. v. i.
author	ARLID cav_un_auth*0101179 name1 Pohl name2 Zdeněk institution UTIA-B full_dept Department of Signal Processing fullinstit Ústav teorie informace a automatizace AV ČR, v. v. i.
COSATI	09G
COSATI	09H
cas_special	project project_id LN00B096 agency GA MŠk ARLID cav_un_auth*0027922 research CEZ:AV0Z1075907 abstract (eng) Poster describes an algorithm development process for FPGA. The process is shown on the example of an implementation of the QR RLS algorithm. action ARLID cav_un_auth*0212938 name International Student Conference on Electrical Engineering /6./ place Praha country CZ dates 23.05.2002 RIV JC department ZS permalink http://hdl.handle.net/11104/0130953 ID_orig UTIA-B 20020080 arlyear 2002 mrcbU10 2002 mrcbU10 Praha FEL ČVUT mrcbU63 POSTER 2002 2