bibtype C - Conference Paper (international conference)
ARLID 0410868
utime 20240103182245.0
mtime 20060210235959.9
title (primary) (eng) Floating-Point-Like Arithmetic for FPGA
publisher
place Praha
name FEL ČVUT
pub_time 2002
specification
page_count 1 s.
serial
title POSTER 2002
page_num 2
keyword HSLA, RLS, LNS
keyword IP core, DSP
author (primary)
ARLID cav_un_auth*0101159
name1 Matoušek
name2 Rudolf
institution UTIA-B
fullinstit Ústav teorie informace a automatizace AV ČR, v. v. i.
author
ARLID cav_un_auth*0101152
name1 Líčko
name2 Miroslav
institution UTIA-B
fullinstit Ústav teorie informace a automatizace AV ČR, v. v. i.
author
ARLID cav_un_auth*0101105
name1 Heřmánek
name2 Antonín
institution UTIA-B
fullinstit Ústav teorie informace a automatizace AV ČR, v. v. i.
author
ARLID cav_un_auth*0212939
name1 Softley
name2 C.
country GB
COSATI 09G
COSATI 09H
cas_special
project
project_id LN00B096
agency GA MŠk
ARLID cav_un_auth*0027922
project
project_id 33544
agency ESPRIT
country XE
research CEZ:AV0Z1075907
abstract (eng) In recent years we have investigated the use of a logarithmic number representation as an alternative to floating-point. Efficient techniques have been developed to facilitate arithmetic comparable to single precision floating-point in the logarithmic domain.
action
ARLID cav_un_auth*0212938
name International Student Conference on Electrical Engineering /6./
place Praha
country CZ
dates 23.05.2002
RIV JC
department ZS
permalink http://hdl.handle.net/11104/0130955
ID_orig UTIA-B 20020082
arlyear 2002
mrcbU10 2002
mrcbU10 Praha FEL ČVUT
mrcbU63 POSTER 2002 2