bibtype C - Conference Paper (international conference)
ARLID 0410916
utime 20240103182248.5
mtime 20060210235959.9
ISBN 0-7803-7403-7
title (primary) (eng) Pipelined implementations of the A Priory Error-Feedback LSL algorithm using logarithmic arithmetic
part_num 3
publisher
place Orlando
name IEEE
pub_time 2002
specification
page_count 4 s.
serial
title Proceedings of the IEEE International Conference on Acoustics, Speech and Signal Processing
page_num 2681-2684
keyword LNS, DSP, FPGA
keyword floating-point
keyword logarithmic arithmetic
author (primary)
ARLID cav_un_auth*0212813
name1 Albu
name2 F.
country IE
author
ARLID cav_un_auth*0101120
name1 Kadlec
name2 Jiří
institution UTIA-B
full_dept Department of Signal Processing
fullinstit Ústav teorie informace a automatizace AV ČR, v. v. i.
author
ARLID cav_un_auth*0212961
name1 Coleman
name2 N.
country GB
author
ARLID cav_un_auth*0212814
name1 Fagan
name2 A.
country IE
COSATI 09G
COSATI 09H
cas_special
project
project_id 33544
agency ESPRIT
country XE
research CEZ:AV0Z1075907
abstract (eng) In this paper we present several implementations of the Modified A Priori Error-Feedback LSL (EF-LSL) algorithm on the Virtex FPGA. Its computational parallelism and pipelinabilty are important advantages. Internally, the computations are based on the logarithmic number system. We compare 32-bit (SINGLE-ALU or DUAL-ALU version) and 20-bit (QUADRI-ALU versions). We show that the LNS implementation can outperform the standard DSP solution based on 32-bit floating-point processors.
action
ARLID cav_un_auth*0212908
name ICASSP 2002
place Orlando
country US
dates 13.05.2002-17.05.2002
RIV JC
department ZS
permalink http://hdl.handle.net/11104/0131003
ID_orig UTIA-B 20020130
arlyear 2002
mrcbU10 2002
mrcbU10 Orlando IEEE
mrcbU12 0-7803-7403-7
mrcbU63 Proceedings of the IEEE International Conference on Acoustics, Speech and Signal Processing 2681 2684