bibtype C - Conference Paper (international conference)
ARLID 0410974
utime 20240103182252.7
mtime 20060210235959.9
ISBN 80-7080-500-5
title (primary) (eng) Extension for Xilinx System Generator - logarithmic arithmetic blockset
part_num 1
publisher
place Praha
name VŠCHT
pub_time 2002
specification
page_count 5 s.
serial
title MATLAB 2002. Sborník příspěvků 10. ročníku konference
page_num 280-284
keyword Xilinx System Generator
keyword field programmable gate arrays
keyword MATLAB/Simulink
author (primary)
ARLID cav_un_auth*0101152
name1 Líčko
name2 Miroslav
institution UTIA-B
fullinstit Ústav teorie informace a automatizace AV ČR, v. v. i.
author
ARLID cav_un_auth*0212986
name1 Métais
name2 B.
country FR
author
ARLID cav_un_auth*0101213
name1 Tichý
name2 Milan
institution UTIA-B
fullinstit Ústav teorie informace a automatizace AV ČR, v. v. i.
author
ARLID cav_un_auth*0101159
name1 Matoušek
name2 Rudolf
institution UTIA-B
fullinstit Ústav teorie informace a automatizace AV ČR, v. v. i.
COSATI 09H
COSATI 09G
cas_special
project
project_id LN00B096
agency GA MŠk
ARLID cav_un_auth*0027922
research CEZ:AV0Z1075907
abstract (eng) The paper introduces support of floating point(FP) data format for the Xilinx System Generator (XSG) using logarithmic arithmetic. This type of arithmetic seems to be one of the promising ways to solve FP sort of DSP problems in practice. Our 32-bit high-speed logarithmic arithmetic (HSLA) keeps the accuracy according to IEEE 754 and speed up some kinds of FP algorithms. Promising is 19-bit equivalent utilised int this paper. It offers reasonable precision for the practical use and has min.HW requirements.
action
ARLID cav_un_auth*0212971
name MATLAB 2002
place Praha
country CZ
dates 07.11.2002
RIV JC
department ZS
permalink http://hdl.handle.net/11104/0131061
ID_orig UTIA-B 20020188
arlyear 2002
mrcbU10 2002
mrcbU10 Praha VŠCHT
mrcbU12 80-7080-500-5
mrcbU63 MATLAB 2002. Sborník příspěvků 10. ročníku konference 280 284 MATLAB 2002. Proceedings of the 10th conference