bibtype |
C -
Conference Paper (international conference)
|
ARLID |
0410975 |
utime |
20240103182252.8 |
mtime |
20060210235959.9 |
ISBN |
80-7080-500-5 |
title
(primary) (eng) |
Utilization of the HSLA toolbox for the FPGA prototyping |
part_num |
2 |
publisher |
place |
Praha |
name |
VŠCHT |
pub_time |
2002 |
|
specification |
|
serial |
title
|
MATLAB 2002. Sborník příspěvků 10. ročníku konference |
page_num |
462-468 |
|
keyword |
design flow for DSP algorithms |
keyword |
high-speed logarithmic arithmetic |
author
(primary) |
ARLID |
cav_un_auth*0101179 |
name1 |
Pohl |
name2 |
Zdeněk |
institution |
UTIA-B |
full_dept |
Department of Signal Processing |
fullinstit |
Ústav teorie informace a automatizace AV ČR, v. v. i. |
|
author
|
ARLID |
cav_un_auth*0212893 |
name1 |
Líčko |
name2 |
M. |
country |
CZ |
|
COSATI |
09G |
COSATI |
09H |
cas_special |
project |
project_id |
33544 |
agency |
ESPRIT |
country |
XE |
|
project |
project_id |
LN00B096 |
agency |
GA MŠk |
ARLID |
cav_un_auth*0027922 |
|
research |
CEZ:AV0Z1075907 |
abstract
(eng) |
An innovative design-flow for DSP algorithms usign high-speed logarithmic arithmetic (HSLA) toolbox is introduced on a demo RLS lattice application. Utilization of toolbox provides effective design time shortening and it makes designer work easier. Firstly, scripts in Matlab are written and checked. From working scripts, design is decomposed in Simulink to cycle-exact simulation and rewritten in Celoxica DK1 tool. Finally, hardware is targeted from DK1 and results are compared with simulations. |
action |
ARLID |
cav_un_auth*0212971 |
name |
MATLAB 2002 |
place |
Praha |
country |
CZ |
dates |
07.11.2002 |
|
RIV |
JC |
department |
ZS |
permalink |
http://hdl.handle.net/11104/0131062 |
ID_orig |
UTIA-B 20020189 |
arlyear |
2002 |
mrcbU10 |
2002 |
mrcbU10 |
Praha VŠCHT |
mrcbU12 |
80-7080-500-5 |
mrcbU63 |
MATLAB 2002. Sborník příspěvků 10. ročníku konference 462 468 MATLAB 2002. Proceedings of the 10th conference |
|