| bibtype |
C -
Conference Paper (international conference)
|
| ARLID |
0411039 |
| utime |
20240103182257.4 |
| mtime |
20060210235959.9 |
| ISBN |
1-58113-651-X |
| title
(primary) (eng) |
Lattice adaptive filter implementation for FPGA |
| publisher |
| place |
Monterey |
| name |
ACM |
| pub_time |
2003 |
|
| specification |
|
| serial |
| title
|
FPGA 2003 ACM/SIGDA Eleventh ACM International Symposium on Field-Programmable Gate Arrays |
| page_num |
246 |
|
| keyword |
lattice adaptive filter |
| keyword |
FPGA |
| author
(primary) |
| ARLID |
cav_un_auth*0101179 |
| name1 |
Pohl |
| name2 |
Zdeněk |
| institution |
UTIA-B |
| full_dept |
Department of Signal Processing |
| fullinstit |
Ústav teorie informace a automatizace AV ČR, v. v. i. |
|
| author
|
| ARLID |
cav_un_auth*0101159 |
| name1 |
Matoušek |
| name2 |
Rudolf |
| institution |
UTIA-B |
| fullinstit |
Ústav teorie informace a automatizace AV ČR, v. v. i. |
|
| author
|
| ARLID |
cav_un_auth*0101120 |
| name1 |
Kadlec |
| name2 |
Jiří |
| institution |
UTIA-B |
| full_dept |
Department of Signal Processing |
| fullinstit |
Ústav teorie informace a automatizace AV ČR, v. v. i. |
|
| author
|
| ARLID |
cav_un_auth*0101213 |
| name1 |
Tichý |
| name2 |
Milan |
| institution |
UTIA-B |
| fullinstit |
Ústav teorie informace a automatizace AV ČR, v. v. i. |
|
| author
|
| ARLID |
cav_un_auth*0212893 |
| name1 |
Líčko |
| name2 |
M. |
| country |
CZ |
|
| COSATI |
09G |
| COSATI |
09H |
| cas_special |
| project |
| project_id |
LN00B096 |
| agency |
GA MŠk |
| ARLID |
cav_un_auth*0027922 |
|
| research |
CEZ:AV0Z1075907 |
| abstract
(eng) |
Our poster introduces an innovative RLS Lattice filter implementation for FPGAs. The signal processing applications typically require wide numeric range, and that poses a problem when using an FPGA implementation. Our aaproach is based on arithmetic using logarithmic numeric representation (LNS). The test application - adaptive noise canceller - has been optimized for the Xilinx Virtex devices. It consumes roughly 70% of all logic resources of the XCV800 device and all block memory cells. |
| action |
| ARLID |
cav_un_auth*0213010 |
| name |
FPGA 2003 |
| place |
Monterey |
| country |
US |
| dates |
23.02.2003-25.02.2003 |
|
| RIV |
JC |
| department |
ZS |
| permalink |
http://hdl.handle.net/11104/0131126 |
| ID_orig |
UTIA-B 20030026 |
| arlyear |
2003 |
| mrcbU10 |
2003 |
| mrcbU10 |
Monterey ACM |
| mrcbU12 |
1-58113-651-X |
| mrcbU63 |
FPGA 2003 ACM/SIGDA Eleventh ACM International Symposium on Field-Programmable Gate Arrays 246 |
|