| bibtype |
C -
Conference Paper (international conference)
|
| ARLID |
0411120 |
| utime |
20240103182303.3 |
| mtime |
20060210235959.9 |
| ISBN |
3-540-40822-3 |
| title
(primary) (eng) |
FPGA implementation of the adaptive lattice filter |
| publisher |
| place |
Berlin |
| name |
Springer |
| pub_time |
2003 |
|
| specification |
|
| edition |
| name |
Lecture Notes in Computer Science. |
| volume_id |
2778 |
|
| serial |
| title
|
Field-Programmable Logic and Applications. Proceedings of the 13th International Conference |
| page_num |
1095-1098 |
| editor |
| name1 |
Cheung |
| name2 |
P. Y. K. |
|
| editor |
| name1 |
Constantinides |
| name2 |
G. A. |
|
| editor |
| name1 |
de Sousa |
| name2 |
J. D. |
|
|
| keyword |
FPGA |
| keyword |
logarithmic numbering system |
| keyword |
floating-point signal processor |
| author
(primary) |
| ARLID |
cav_un_auth*0101105 |
| name1 |
Heřmánek |
| name2 |
Antonín |
| institution |
UTIA-B |
| fullinstit |
Ústav teorie informace a automatizace AV ČR, v. v. i. |
|
| author
|
| ARLID |
cav_un_auth*0101179 |
| name1 |
Pohl |
| name2 |
Zdeněk |
| institution |
UTIA-B |
| full_dept |
Department of Signal Processing |
| fullinstit |
Ústav teorie informace a automatizace AV ČR, v. v. i. |
|
| author
|
| ARLID |
cav_un_auth*0101120 |
| name1 |
Kadlec |
| name2 |
Jiří |
| institution |
UTIA-B |
| full_dept |
Department of Signal Processing |
| fullinstit |
Ústav teorie informace a automatizace AV ČR, v. v. i. |
|
| COSATI |
09G |
| COSATI |
09H |
| cas_special |
| project |
| project_id |
IST-2001-34016 |
| agency |
EU IST |
| country |
XE |
| ARLID |
cav_un_auth*0200683 |
|
| project |
| project_id |
LN00B096 |
| agency |
GA MŠk |
| ARLID |
cav_un_auth*0027922 |
|
| research |
CEZ:AV0Z1075907 |
| abstract
(eng) |
This paper presents the FPGA implementation of a noise canceler with an adaptive RLS-Lattice filter in Xilinx devices. Since this algorithm requires floating-point computations, Logarithmic Numbering System (LNS) has been used. The pipelined lattice filter macro and input/output conversion routines has been designed. The implementation results are compared with an implementation on 32-bit IEEE floating-point signal processor. |
| action |
| ARLID |
cav_un_auth*0213049 |
| name |
Field Programmable Logic and Applications /13./ |
| place |
Lisabon |
| country |
PT |
| dates |
01.09.2003-03.09.2003 |
|
| RIV |
JC |
| department |
ZS |
| permalink |
http://hdl.handle.net/11104/0131207 |
| ID_orig |
UTIA-B 20030107 |
| arlyear |
2003 |
| mrcbU10 |
2003 |
| mrcbU10 |
Berlin Springer |
| mrcbU12 |
3-540-40822-3 |
| mrcbU63 |
Field-Programmable Logic and Applications. Proceedings of the 13th International Conference 1095 1098 |
| mrcbU67 |
Cheung P. Y. K. 340 |
| mrcbU67 |
Constantinides G. A. 340 |
| mrcbU67 |
de Sousa J. D. 340 |
|