| bibtype |
C -
Conference Paper (international conference)
|
| ARLID |
0411121 |
| utime |
20240103182303.4 |
| mtime |
20060210235959.9 |
| ISBN |
3-540-40822-3 |
| title
(primary) (eng) |
MATLAB/Simulink based methodology for rapid-FPGA-prototyping |
| publisher |
| place |
Berlin |
| name |
Springer |
| pub_time |
2003 |
|
| specification |
|
| edition |
| name |
Lecture Notes in Computer Science. |
| volume_id |
2778 |
|
| serial |
| title
|
Field-Programmable Logic and Applications. Proceedings of the 13th International Conference |
| page_num |
984-987 |
| editor |
| name1 |
Cheung |
| name2 |
P. Y. K. |
|
| editor |
| name1 |
Constantinides |
| name2 |
G. A. |
|
| editor |
| name1 |
de Sousa |
| name2 |
J. T. |
|
|
| keyword |
Matlab |
| keyword |
Simulink |
| keyword |
FPGA |
| author
(primary) |
| ARLID |
cav_un_auth*0101152 |
| name1 |
Líčko |
| name2 |
Miroslav |
| institution |
UTIA-B |
| fullinstit |
Ústav teorie informace a automatizace AV ČR, v. v. i. |
|
| author
|
| ARLID |
cav_un_auth*0101190 |
| name1 |
Schier |
| name2 |
Jan |
| institution |
UTIA-B |
| full_dept |
Department of Image Processing |
| fullinstit |
Ústav teorie informace a automatizace AV ČR, v. v. i. |
|
| author
|
| ARLID |
cav_un_auth*0101213 |
| name1 |
Tichý |
| name2 |
Milan |
| institution |
UTIA-B |
| fullinstit |
Ústav teorie informace a automatizace AV ČR, v. v. i. |
|
| author
|
| ARLID |
cav_un_auth*0213050 |
| name1 |
Kühl |
| name2 |
M. |
| country |
DE |
|
| COSATI |
09G |
| COSATI |
09H |
| cas_special |
| project |
| project_id |
2001-34016 |
| agency |
IST |
| country |
XE |
|
| project |
| project_id |
KONTAKT CZE01/019 |
| agency |
GA MŠk |
| ARLID |
cav_un_auth*0213052 |
|
| project |
| project_id |
LN00B096 |
| agency |
GA MŠk |
| ARLID |
cav_un_auth*0027922 |
|
| research |
CEZ:AV0Z1075907 |
| abstract
(eng) |
The paper is focused on rapid prototyping for FPGA using the high-level environment of MATLAB/Simulink. An approach using combination of the Xilinx System Generator (XSG) and Handel-C is rewieved. A design flow to minimize HDL coding is considered. |
| action |
| ARLID |
cav_un_auth*0213051 |
| name |
Field-Programmable Logic and Applications /13./ |
| place |
Lisabon |
| country |
PT |
| dates |
01.09.2003-03.09.2003 |
|
| RIV |
JC |
| department |
ZS |
| permalink |
http://hdl.handle.net/11104/0131208 |
| ID_orig |
UTIA-B 20030108 |
| arlyear |
2003 |
| mrcbU10 |
2003 |
| mrcbU10 |
Berlin Springer |
| mrcbU12 |
3-540-40822-3 |
| mrcbU63 |
Field-Programmable Logic and Applications. Proceedings of the 13th International Conference 984 987 |
| mrcbU67 |
Cheung P. Y. K. 340 |
| mrcbU67 |
Constantinides G. A. 340 |
| mrcbU67 |
de Sousa J. T. 340 |
|