bibtype |
C -
Conference Paper (international conference)
|
ARLID |
0411172 |
utime |
20240103182307.0 |
mtime |
20060210235959.9 |
title
(primary) (eng) |
FPGA Prototyping Using Extensions to MATLAB/Simulink |
publisher |
place |
Southampton |
name |
University of Southampton |
pub_time |
2003 |
|
specification |
|
serial |
title
|
UK ACM SIGDA 3rd Workshop on Electronic Design Automation |
page_num |
1-3 |
editor |
name1 |
Hettiaratchi |
name2 |
S. |
|
|
keyword |
rapid prototyping |
keyword |
FPGA |
keyword |
MATLAB/Simulink |
author
(primary) |
ARLID |
cav_un_auth*0101152 |
name1 |
Líčko |
name2 |
Miroslav |
institution |
UTIA-B |
fullinstit |
Ústav teorie informace a automatizace AV ČR, v. v. i. |
|
author
|
ARLID |
cav_un_auth*0101190 |
name1 |
Schier |
name2 |
Jan |
institution |
UTIA-B |
full_dept |
Department of Image Processing |
fullinstit |
Ústav teorie informace a automatizace AV ČR, v. v. i. |
|
COSATI |
09G |
COSATI |
09H |
cas_special |
project |
project_id |
IST-2001-34016 |
agency |
Commission EC |
country |
XE |
ARLID |
cav_un_auth*0200683 |
|
project |
project_id |
LN00B096 |
agency |
GA MŠk |
ARLID |
cav_un_auth*0027922 |
|
research |
CEZ:AV0Z1075907 |
abstract
(eng) |
Rapid prototyping for FPGAs using high-level environment of MATLAB/Simulink is addressed in this paper. An approach using combination of the Xilinx System Generator (XSG) and Handel-C is given. A design flow to minimize HDL coding is considered. |
action |
ARLID |
cav_un_auth*0213093 |
name |
UK ACM SIGDA Workshop on Electronic Design Automation /3./ |
place |
Southampton |
country |
GB |
dates |
11.09.2003-12.09.2003 |
|
RIV |
JC |
department |
ZS |
permalink |
http://hdl.handle.net/11104/0131258 |
ID_orig |
UTIA-B 20030159 |
arlyear |
2003 |
mrcbU10 |
2003 |
mrcbU10 |
Southampton University of Southampton |
mrcbU63 |
UK ACM SIGDA 3rd Workshop on Electronic Design Automation 1 3 |
mrcbU67 |
Hettiaratchi S. 340 |
|