bibtype E - Electronic Document
ARLID 0411193
utime 20240111140636.2
mtime 20060210235959.9
title (primary) (eng) Lattice IP Core used in Real-time Lattice Demo on XESS Board. (Program)
publisher
place Praha
name ÚTIA AV ČR
pub_time 2003
specification
media_type CD-ROM
keyword RLS Lattice
keyword FPGA
keyword noise cancelation
author (primary)
ARLID cav_un_auth*0101179
name1 Pohl
name2 Zdeněk
institution UTIA-B
full_dept Department of Signal Processing
fullinstit Ústav teorie informace a automatizace AV ČR, v. v. i.
author
ARLID cav_un_auth*0101120
name1 Kadlec
name2 Jiří
institution UTIA-B
full_dept Department of Signal Processing
fullinstit Ústav teorie informace a automatizace AV ČR, v. v. i.
author
ARLID cav_un_auth*0101152
name1 Líčko
name2 Miroslav
institution UTIA-B
fullinstit Ústav teorie informace a automatizace AV ČR, v. v. i.
author
ARLID cav_un_auth*0101159
name1 Matoušek
name2 Rudolf
institution UTIA-B
fullinstit Ústav teorie informace a automatizace AV ČR, v. v. i.
author
ARLID cav_un_auth*0101213
name1 Tichý
name2 Milan
institution UTIA-B
fullinstit Ústav teorie informace a automatizace AV ČR, v. v. i.
source
source_type program
source_size 32 MB
COSATI 09G
COSATI 09H
cas_special
project
project_id LN00B096
agency GA MŠk
ARLID cav_un_auth*0027922
research CEZ:AV0Z1075907
abstract (eng) A demo for XSV-800 board from XESS corporation. A 10-bit logarithmic arithmetic is used for implementation of a high performance DSP application. It is performing noise cancelation for audio signals from audiocodec inputs and wieting output to the audio output. The demo is possible to be downloaped from the UTIA website.
RIV JC
department ZS
permalink http://hdl.handle.net/11104/0131279
ID_orig UTIA-B 20030180
arlyear 2003
mrcbU10 2003
mrcbU10 Praha ÚTIA AV ČR
mrcbU56 program 32 MB