| bibtype |
K -
Conference Paper (Czech conference)
|
| ARLID |
0411196 |
| utime |
20240103182309.0 |
| mtime |
20060210235959.9 |
| ISBN |
80-214-2471-0 |
| title
(primary) (eng) |
Integrated iterative approach to FPGA placement |
| publisher |
| place |
Brno |
| name |
VUT |
| pub_time |
2003 |
|
| specification |
|
| serial |
| title
|
Počítačové Architektury & Diagnostika PAD 2003 |
| page_num |
43-50 |
| editor |
|
| editor |
|
| editor |
|
|
| keyword |
FPGA placement |
| keyword |
global routing |
| keyword |
integrated approach |
| author
(primary) |
| ARLID |
cav_un_auth*0101077 |
| name1 |
Daněk |
| name2 |
Martin |
| institution |
UTIA-B |
| fullinstit |
Ústav teorie informace a automatizace AV ČR, v. v. i. |
|
| COSATI |
09G |
| COSATI |
09H |
| cas_special |
| project |
| project_id |
0210413 |
| agency |
CTU |
| country |
CZ |
|
| research |
CEZ:AV0Z1075907 |
| abstract
(eng) |
This paper describes a new iterative method based on an integrated timing-driven approach to the FPGA layout synthesis. The method uses a global routing to assess the quality of a placement. The placement and routing algorithms use an unified nonlinear cost function that takes into account both area and delay constraints imposed by a design, and eliminates effects of different signal net routing orders. |
| action |
| ARLID |
cav_un_auth*0213111 |
| name |
PAD 2003 Počítačové Architektury & Diagnostika |
| place |
Zvíkovské Podhradí |
| country |
CZ |
| dates |
24.09.2003-26.09.2003 |
|
| RIV |
JC |
| department |
ZS |
| permalink |
http://hdl.handle.net/11104/0131282 |
| ID_orig |
UTIA-B 20030183 |
| arlyear |
2003 |
| mrcbU10 |
2003 |
| mrcbU10 |
Brno VUT |
| mrcbU12 |
80-214-2471-0 |
| mrcbU63 |
Počítačové Architektury & Diagnostika PAD 2003 43 50 |
| mrcbU67 |
Kotásek Z. 340 |
| mrcbU67 |
Růžička R. 340 |
| mrcbU67 |
Sekanina L. 340 |
|