| bibtype |
C -
Conference Paper (international conference)
|
| ARLID |
0411202 |
| utime |
20240111140636.2 |
| mtime |
20060210235959.9 |
| ISBN |
0-7695-1926-1 |
| title
(primary) (eng) |
Logarithmic arithmetic for real data types and support for Matlab/Simulink based rapid-FPGA-prototyping |
| publisher |
| place |
Los Alamitos |
| name |
IEEE Computer Society Press |
| pub_time |
2003 |
|
| specification |
|
| serial |
| title
|
Proceedings of the International Parallel and Distributed Processing Symposium. IPDPS 2003 |
| page_num |
1-6 |
| editor |
|
|
| keyword |
high speed logarithmic arithmetic |
| keyword |
Matlab/Simulink |
| keyword |
rapid prototyping |
| author
(primary) |
| ARLID |
cav_un_auth*0101179 |
| name1 |
Pohl |
| name2 |
Zdeněk |
| institution |
UTIA-B |
| full_dept |
Department of Signal Processing |
| fullinstit |
Ústav teorie informace a automatizace AV ČR, v. v. i. |
|
| author
|
| ARLID |
cav_un_auth*0101190 |
| name1 |
Schier |
| name2 |
Jan |
| institution |
UTIA-B |
| full_dept |
Department of Image Processing |
| fullinstit |
Ústav teorie informace a automatizace AV ČR, v. v. i. |
|
| author
|
| ARLID |
cav_un_auth*0101152 |
| name1 |
Líčko |
| name2 |
Miroslav |
| institution |
UTIA-B |
| fullinstit |
Ústav teorie informace a automatizace AV ČR, v. v. i. |
|
| author
|
| ARLID |
cav_un_auth*0101105 |
| name1 |
Heřmánek |
| name2 |
Antonín |
| institution |
UTIA-B |
| fullinstit |
Ústav teorie informace a automatizace AV ČR, v. v. i. |
|
| author
|
| ARLID |
cav_un_auth*0101213 |
| name1 |
Tichý |
| name2 |
Milan |
| institution |
UTIA-B |
| fullinstit |
Ústav teorie informace a automatizace AV ČR, v. v. i. |
|
| source |
|
| COSATI |
09G |
| COSATI |
09H |
| cas_special |
| project |
| project_id |
IST-2001-34016 |
| agency |
Commission EC |
| country |
XE |
| ARLID |
cav_un_auth*0200683 |
|
| project |
| project_id |
LN00B096 |
| agency |
GA MŠk |
| ARLID |
cav_un_auth*0027922 |
|
| research |
CEZ:AV0Z1075907 |
| abstract
(eng) |
The paper is focused on the rapid prototyping for FPGA using the high-level environment of MATLAB/Simulink. An approach using the Xilinx system Generator is reviewed on an example of the High Speed Logaritmic Arithmetic unit. An alternative approach using the combination of the real time workshop with the Handel C compiler for automatized generation of the HDL code is presented. The possibilities to extend this solution in order to support the run-time reconfigurations are outlined. |
| action |
| ARLID |
cav_un_auth*0213114 |
| name |
IEEE IPDPS 2003 |
| place |
Nice |
| country |
FR |
| dates |
22.04.2003-26.04.2003 |
|
| RIV |
JC |
| department |
ZS |
| permalink |
http://hdl.handle.net/11104/0131288 |
| ID_orig |
UTIA-B 20030189 |
| arlyear |
2003 |
| mrcbU10 |
2003 |
| mrcbU10 |
Los Alamitos IEEE Computer Society Press |
| mrcbU12 |
0-7695-1926-1 |
| mrcbU56 |
149 kB |
| mrcbU63 |
Proceedings of the International Parallel and Distributed Processing Symposium. IPDPS 2003 1 6 |
| mrcbU67 |
Werner B. 340 |
|