| bibtype |
J -
Journal Article
|
| ARLID |
0411292 |
| utime |
20240103182316.1 |
| mtime |
20060210235959.9 |
| title
(primary) (eng) |
Reconfigurable system on programmable chip platform |
| specification |
|
| serial |
| title
|
ATMEL Applications Journal |
| page_num |
9-12 |
|
| title
(cze) |
Rekonfigurovatelný systém pro programovatelný integrovaný obvod |
| keyword |
reconfigurable system |
| keyword |
FPGA |
| author
(primary) |
| ARLID |
cav_un_auth*0101077 |
| name1 |
Daněk |
| name2 |
Martin |
| institution |
UTIA-B |
| fullinstit |
Ústav teorie informace a automatizace AV ČR, v. v. i. |
|
| author
|
| ARLID |
cav_un_auth*0108102 |
| name1 |
Honzík |
| name2 |
Petr |
| institution |
UTIA-B |
| fullinstit |
Ústav teorie informace a automatizace AV ČR, v. v. i. |
|
| author
|
| ARLID |
cav_un_auth*0101120 |
| name1 |
Kadlec |
| name2 |
Jiří |
| institution |
UTIA-B |
| full_dept |
Department of Signal Processing |
| fullinstit |
Ústav teorie informace a automatizace AV ČR, v. v. i. |
|
| author
|
| ARLID |
cav_un_auth*0101159 |
| name1 |
Matoušek |
| name2 |
Rudolf |
| institution |
UTIA-B |
| fullinstit |
Ústav teorie informace a automatizace AV ČR, v. v. i. |
|
| author
|
| ARLID |
cav_un_auth*0101179 |
| name1 |
Pohl |
| name2 |
Zdeněk |
| institution |
UTIA-B |
| full_dept |
Department of Signal Processing |
| fullinstit |
Ústav teorie informace a automatizace AV ČR, v. v. i. |
|
| COSATI |
09G |
| COSATI |
09H |
| cas_special |
| project |
| project_id |
IST-2001-34016 |
| agency |
EU FP5 IST Programme |
| country |
XE |
| ARLID |
cav_un_auth*0200683 |
|
| project |
| project_id |
GA102/04/2137 |
| agency |
GA ČR |
| ARLID |
cav_un_auth*0004198 |
|
| research |
CEZ:AV0Z10750506 |
| abstract
(eng) |
This paper presents an universal reconfigurable SOPC platform based on a combination of the Atmel AT94K FPSLIC device and an external memory. The presented platform increases the power of the FPSLIC device both by extending the internal address space through an introduction of a virtual program memory and by providing a transparent infrastructure for FPGA reconfiguration. The platform is demonstrated on two simple designs that demonstrate both aspects. |
| abstract
(cze) |
Článek popisuje podporu pro universální mikroprocesor kombinovaný s programovatelným logickým obvodem na jediném čipu FPSLIC. Podpora dovoluje částečnou rekonfiguraci. |
| RIV |
JC |
| reportyear |
2006 |
| department |
ZS |
| permalink |
http://hdl.handle.net/11104/0131375 |
| ID_orig |
UTIA-B 20050020 |
| arlyear |
2005 |
| mrcbU63 |
ATMEL Applications Journal č. 4 2005 9 12 |
|