| bibtype |
A -
Abstract
|
| ARLID |
0411302 |
| utime |
20240103182316.8 |
| mtime |
20060210235959.9 |
| ISBN |
1-59593-029-9 |
| title
(primary) (eng) |
VPart: An automatic partitioning tool for dynamic reconfiguration. Abstract |
| publisher |
| place |
Monterey |
| name |
ACM |
| pub_time |
2005 |
|
| specification |
|
| serial |
| title
|
FPGA 2005 - ACM/SIGDA Thirteenth International Symposium on Field-Programmable Gate Arrays |
| page_num |
263 |
| editor |
|
| editor |
|
|
| title
(cze) |
VPart: Nástroj pro automatické rozdělení návrhu umožňující dynamickou rekonfiguraci. Abstrakt |
| keyword |
automatic partitioning |
| keyword |
reconfiguration |
| keyword |
design tools |
| author
(primary) |
| ARLID |
cav_un_auth*0202863 |
| name1 |
Kafka |
| name2 |
Leoš |
| institution |
UTIA-B |
| fullinstit |
Ústav teorie informace a automatizace AV ČR, v. v. i. |
|
| author
|
| ARLID |
cav_un_auth*0213168 |
| name1 |
Kielbik |
| name2 |
R. |
| country |
PL |
|
| author
|
| ARLID |
cav_un_auth*0101159 |
| name1 |
Matoušek |
| name2 |
Rudolf |
| institution |
UTIA-B |
| fullinstit |
Ústav teorie informace a automatizace AV ČR, v. v. i. |
|
| author
|
| ARLID |
cav_un_auth*0213169 |
| name1 |
Moreno |
| name2 |
J. M. |
| country |
ES |
|
| COSATI |
09G |
| COSATI |
09H |
| cas_special |
| project |
| project_id |
LN00B096 |
| agency |
GA MŠk |
| ARLID |
cav_un_auth*0027922 |
|
| project |
| project_id |
IST-2001-34016 |
| agency |
IST FP5 |
| country |
XE |
| ARLID |
cav_un_auth*0200683 |
|
| research |
CEZ:AV0Z10750506 |
| abstract
(eng) |
This paper presents an innovative tool for automatic partitioning of VHDL designs for dynamic reconfiguration called VPart. An introduction to the dynamic implementation of a circuit is presented. A design flow and optimization algorithms and methods used by the tool to partition the input design are explained. The usage of the tool is shown on three simple experiments performed on 18-bit floating-point arithmetic adder and multiplier. |
| abstract
(cze) |
Tento text prezentuje nástroj pro automatické rozdělení VHDL návrhu umožňující dynamickou rekonfiguraci. Úvod je věnován dynamické implementaci obvodů. Dále vysvětluje postup návrhu a optimalizaci algoritmů a metod použitých tímto nástrojem. Použití nástroje je předvedeno na třech jednoduchých příkladech s 18-bitovou sčítačkou a násobičkou pro čísla s pohyblivou řádovou čárkou. |
| action |
| ARLID |
cav_un_auth*0213166 |
| name |
FPGA 2005 /13./ |
| place |
Monterey |
| country |
US |
| dates |
20.02.2005-22.02.2005 |
|
| RIV |
JC |
| reportyear |
2006 |
| department |
ZS |
| permalink |
http://hdl.handle.net/11104/0131385 |
| ID_orig |
UTIA-B 20050030 |
| arlyear |
2005 |
| mrcbU10 |
2005 |
| mrcbU10 |
Monterey ACM |
| mrcbU12 |
1-59593-029-9 |
| mrcbU63 |
FPGA 2005 - ACM/SIGDA Thirteenth International Symposium on Field-Programmable Gate Arrays 263 |
| mrcbU67 |
Schmidt H. 340 |
| mrcbU67 |
Wilton S. 340 |
|