bibtype	C - Conference Paper (international conference)
ARLID	0411311
utime	20240103182317.4
mtime	20060210235959.9
ISBN	963-9364-48-7
title (primary) (eng)	Dynamic reconfiguration in FPGA-based SoC designs
publisher	place Sopron name University of West Hungary pub_time 2005
specification	page_count 8 s.
serial	title Proceedings of the 8th IEEE Workshop on Designs and Diagnostics of Electronic Circuits nad Systems page_num 129-136 editor name1 Takách name2 G. editor name1 Hlawiczka name2 A. editor name1 Sziraj name2 J.
title (cze)	Dynamická rekonfigurace v FPGA systémech na jednom čipu
keyword	FPGA
keyword	dynamic reconfiguration
author (primary)	ARLID cav_un_auth*0202591 name1 Bartosinski name2 Roman institution UTIA-B fullinstit Ústav teorie informace a automatizace AV ČR, v. v. i.
author	ARLID cav_un_auth*0101077 name1 Daněk name2 Martin institution UTIA-B fullinstit Ústav teorie informace a automatizace AV ČR, v. v. i.
author	ARLID cav_un_auth*0108102 name1 Honzík name2 Petr institution UTIA-B fullinstit Ústav teorie informace a automatizace AV ČR, v. v. i.
author	ARLID cav_un_auth*0101159 name1 Matoušek name2 Rudolf institution UTIA-B fullinstit Ústav teorie informace a automatizace AV ČR, v. v. i.
COSATI	09G
COSATI	09H
cas_special	project project_id IST-2001-34016 agency Commission EC country XE ARLID cav_un_auth*0200683 project project_id 1M0567 agency GA MŠk ARLID cav_un_auth*0202350 research CEZ:AV0Z10750506 abstract (eng) This paper discusses architectural issues arising from the use of dynamic reconfiguration and shows a possible use of dynamic reconfiguration to extend and accelerate a computation performed in system-on-a-chip designs with microprocessors with fixed instruction sets. Further a sample application is discussed that uses a dynamically reconfigurable FPGA to implement different floating-point calculations in hardware, reconfigured as required by the execution of the user code. abstract (cze) Text ukazuje možnosti dynamické rekonfigurace na SoC paltformách založených na FPGA využívajících procesor s pevnou instrukční sadou. Dále je popsán příklad koprocesoru pro FP matematické operace a jeho implementace na dvě komerčně dostupné platformy. Atmel FPSLIC a Xilinx Virtex2. V poslední části je provedeno porovnání obou platforem z několika hledisek vztahujících se k dynamické rekonfiguraci. action ARLID cav_un_auth*0213173 name IEEE Design and Diagnostics of Electronic Circuits nad Systems Workshop (DDECS 2005) /8./ place Sopron country HU dates 13.04.2005-16.04.2005 RIV JC reportyear 2006 department ZS permalink http://hdl.handle.net/11104/0131394 ID_orig UTIA-B 20050039 arlyear 2005 mrcbU10 2005 mrcbU10 Sopron University of West Hungary mrcbU12 963-9364-48-7 mrcbU63 Proceedings of the 8th IEEE Workshop on Designs and Diagnostics of Electronic Circuits nad Systems 129 136 mrcbU67 Takách G. 340 mrcbU67 Hlawiczka A. 340 mrcbU67 Sziraj J. 340