| bibtype |
C -
Conference Paper (international conference)
|
| ARLID |
0411312 |
| utime |
20240111140636.4 |
| mtime |
20060210235959.9 |
| title
(primary) (eng) |
FPGA implementation of Finite Interval CMA |
| publisher |
| place |
Antverpy |
| name |
IEEE |
| pub_time |
2005 |
|
| specification |
| page_count |
3 s. |
| media_type |
CD-ROM |
|
| serial |
| ARLID |
cav_un_epca*0341825 |
| ISBN |
0-7803-9333-3 |
| title
|
Proceedings of the first annual IEEE BENELUX/DSP Valley Signal Processing Symposium. SPS-DARTS 2005 |
| page_num |
97-100 |
| publisher |
| place |
Antverpy |
| name |
IEEE |
| year |
2005 |
|
|
| title
(cze) |
FPGA implementace FI-CMA algoritmu |
| keyword |
CMA algorithm |
| keyword |
FPGA |
| keyword |
data matrix |
| author
(primary) |
| ARLID |
cav_un_auth*0101105 |
| name1 |
Heřmánek |
| name2 |
Antonín |
| institution |
UTIA-B |
| fullinstit |
Ústav teorie informace a automatizace AV ČR, v. v. i. |
|
| author
|
| ARLID |
cav_un_auth*0101190 |
| name1 |
Schier |
| name2 |
Jan |
| institution |
UTIA-B |
| full_dept |
Department of Image Processing |
| fullinstit |
Ústav teorie informace a automatizace AV ČR, v. v. i. |
|
| source |
|
| COSATI |
09G |
| COSATI |
09H |
| COSATI |
09J |
| cas_special |
| project |
| project_id |
1ET300750402 |
| agency |
GA AV ČR |
| ARLID |
cav_un_auth*0001795 |
|
| research |
CEZ:AV0Z10750506 |
| abstract
(eng) |
An FPGA implementation of the FI-CMA algorithm using the Virtex-E and Virtex-II devices is presented. The algorithm consists of two parts: one, performing batch-QR decomposition of the data matrix, and second, used for an iterative equalizer optimization, using the columns of the Q-matrix as input. The resource reuse and minimization of the total latency have been emphasized. Logarithmic arithmetic library has been used for floating point calculations, required in algorithm. |
| abstract
(cze) |
V článku je prezentována FPGA implementace FI-CMA algoritmu s použitím obvodů Virtex-E a Virtex-II. Algoritmus se skládá ze dvou částí: v první se provádí QR rozklad datové matice, v druhé iterativní optimalizace ekvalizátoru, s použitím sloupců matice Q coby vstupu. Návrh je optimalizován s ohledem na vícenásobné využití prostředků a minimalizaci celkové latence. Operace v plovoucí řádové čárce, používané ve výpočtech, byly implementovány s použitím logaritmické aritmetické knihovny. |
| action |
| ARLID |
cav_un_auth*0213174 |
| name |
SPS-DARTS 2005 Signal Processing Symposium /1./ |
| place |
Antverpy |
| country |
BE |
| dates |
19.04.2005-20.04.2005 |
|
| RIV |
JA |
| reportyear |
2010 |
| department |
ZS |
| permalink |
http://hdl.handle.net/11104/0131395 |
| arlyear |
2005 |
| mrcbU10 |
2005 |
| mrcbU10 |
Antverpy IEEE |
| mrcbU56 |
220 kB |
| mrcbU63 |
cav_un_epca*0341825 Proceedings of the first annual IEEE BENELUX/DSP Valley Signal Processing Symposium. SPS-DARTS 2005 0-7803-9333-3 97 100 Antverpy IEEE 2005 |
|