bibtype C - Conference Paper (international conference)
ARLID 0411313
utime 20240103182317.7
mtime 20060210235959.9
ISBN 963-9364-48-7
title (primary) (eng) Fault classification for self-checking circuits implemented in FPGA
publisher
place Sopron
name University of West Hungary
pub_time 2005
specification
page_count 4 s.
serial
title Proceedings of the 8th IEEE Workshop on Design and Diagnostics of Electronics Circuits and Systems
page_num 228-231
editor
name1 Takách
name2 G.
editor
name1 Hlawiczka
name2 A.
editor
name1 Sziray
name2 J.
title (cze) Klasifikace poruch pro samočinně kontrolované obvody
keyword concurrent error detection
keyword FPGA
keyword ED codes
author (primary)
ARLID cav_un_auth*0202863
name1 Kafka
name2 Leoš
institution UTIA-B
fullinstit Ústav teorie informace a automatizace AV ČR, v. v. i.
author
ARLID cav_un_auth*0213175
name1 Kubalík
name2 P.
country CZ
author
ARLID cav_un_auth*0213176
name1 Kubátová
name2 H.
country CZ
author
ARLID cav_un_auth*0045825
name1 Novák
name2 O.
country CZ
COSATI 09G
COSATI 09H
cas_special
project
project_id GA102/04/2137
agency GA ČR
ARLID cav_un_auth*0004198
research CEZ:AV0Z10750506
abstract (eng) This work supports the design process of CED circuits implemented in FPGAs. We propose a new fault classification. We can summarize that our classification leads to a more accurate evaluation of the fault coverage, and we can determine whether the tested circuit satisfies the FS and ST properties. We can also evaluate how many considered faults violate the FS and ST property.
abstract (cze) Článek se zabývá novou klasifikací poruch vhodnou pro samočinně kontrolované obvody. Poruchy jsou rozděleny podle jejich vlivu na bezpečnost proti poruchám a samočinnou kontrolu obvodu, a tak, na rozdíl od běžné klasifikace poruch, umožňuje přesněji vyhodnotit vlastnosti obvodu.
action
ARLID cav_un_auth*0213177
name IEEE Design and Diagnostics of Electronics Circuits and Systems Workshop /8./
place Sopron
country HU
dates 13.04.2005-16.04.2005
RIV JC
reportyear 2006
department ZS
permalink http://hdl.handle.net/11104/0131396
ID_orig UTIA-B 20050041
arlyear 2005
mrcbU10 2005
mrcbU10 Sopron University of West Hungary
mrcbU12 963-9364-48-7
mrcbU63 Proceedings of the 8th IEEE Workshop on Design and Diagnostics of Electronics Circuits and Systems 228 231
mrcbU67 Takách G. 340
mrcbU67 Hlawiczka A. 340
mrcbU67 Sziray J. 340