| bibtype |
L -
Prototype, methodology, f. module, software
|
| ARLID |
0431205 |
| utime |
20240103204549.0 |
| mtime |
20140912235959.9 |
| title
(primary) (eng) |
UTIA EdkDSP Platform Demonstrator on Xilinx SP605 Board – PLB Bus |
| publisher |
|
| keyword |
FPGA |
| keyword |
floating-point accelerator |
| keyword |
PLB bus |
| author
(primary) |
| ARLID |
cav_un_auth*0101120 |
| name1 |
Kadlec |
| name2 |
Jiří |
| full_dept (cz) |
Zpracování signálů |
| full_dept (eng) |
Department of Signal Processing |
| department (cz) |
ZS |
| department (eng) |
ZS |
| institution |
UTIA-B |
| full_dept |
Department of Signal Processing |
| fullinstit |
Ústav teorie informace a automatizace AV ČR, v. v. i. |
|
| source |
|
| cas_special |
| project |
| project_id |
7H12004 |
| agency |
GA MŠk |
| country |
CZ |
| ARLID |
cav_un_auth*0290082 |
|
| abstract
(eng) |
A release version of the EdkDSP package for SP605, PLB bus is offered by UTIA. It provides EdkDSP accelerators for the SP605 in form of PLB netlist pcores with main limitations of the free evaluation package removed. The package contents a ZIP archive with precompiled ISE 14.5 HW projects demonstrating Utia_EdkDSP HW Floating-point accelerators and source code of SDK 14.5 software projects with Utia_EdkDSP libraries. |
| reportyear |
2015 |
| RIV |
JC |
| permalink |
http://hdl.handle.net/11104/0236099 |
| confidential |
C |
| arlyear |
2014 |
| mrcbU10 |
2014 |
|