| bibtype |
L -
Prototype, methodology, f. module, software
|
| ARLID |
0436245 |
| utime |
20240103205204.3 |
| mtime |
20150107235959.9 |
| title
(primary) (eng) |
Interfacing e.MMC 32 GB Memory MTFC32GJWDQ-4M with Xilinx ZC702 FPGA Board |
| publisher |
|
| keyword |
flash memory |
| keyword |
booting of processor |
| keyword |
e.MMC memory controller |
| author
(primary) |
| ARLID |
cav_un_auth*0225749 |
| name1 |
Kohout |
| name2 |
Lukáš |
| full_dept (cz) |
Zpracování signálů |
| full_dept (eng) |
Department of Signal Processing |
| department (cz) |
ZS |
| department (eng) |
ZS |
| institution |
UTIA-B |
| full_dept |
Department of Signal Processing |
| fullinstit |
Ústav teorie informace a automatizace AV ČR, v. v. i. |
|
| author
|
| ARLID |
cav_un_auth*0101160 |
| name1 |
Matulík |
| name2 |
Radim |
| full_dept (cz) |
Zpracování signálů |
| full_dept |
Department of Signal Processing |
| department (cz) |
ZS |
| department |
ZS |
| institution |
UTIA-B |
| full_dept |
Department of Signal Processing |
| fullinstit |
Ústav teorie informace a automatizace AV ČR, v. v. i. |
|
| source |
|
| cas_special |
| project |
| project_id |
7H12004 |
| agency |
GA MŠk |
| country |
CZ |
| ARLID |
cav_un_auth*0290082 |
|
| abstract
(eng) |
This application note describes an interfacing e.MMC32 GB non-volatile memory MTFC32GJWDQ-4M with Xilinx ZC702 FPGA board. The dual core ARM Cortex A9 inside of the ZYNQ part includes 2 SD/e·MC interface cores (SDIO). First core is used for SD card to download bitstream into the FPGA and initiate boot sequence. The second core is not used by default configuration, hence its interface can be used to connect external e.MMC memory. |
| reportyear |
2015 |
| RIV |
JC |
| permalink |
http://hdl.handle.net/11104/0242022 |
| confidential |
S |
| arlyear |
2014 |
| mrcbU10 |
2014 |
|