| bibtype |
L -
Prototype, methodology, f. module, software
|
| ARLID |
0438631 |
| utime |
20240103205445.5 |
| mtime |
20150312235959.9 |
| title
(primary) (eng) |
Computation and Communication Blocks for Xilinx Kintex7 FPGA with UTIA EdkDSP Accelerators. Vivado 2013.4 Designs with SW Demos |
| publisher |
|
| keyword |
floating-point accelerator |
| keyword |
programmable hardware |
| keyword |
signal processing acceleration |
| author
(primary) |
| ARLID |
cav_un_auth*0101120 |
| name1 |
Kadlec |
| name2 |
Jiří |
| full_dept (cz) |
Zpracování signálů |
| full_dept (eng) |
Department of Signal Processing |
| department (cz) |
ZS |
| department (eng) |
ZS |
| institution |
UTIA-B |
| full_dept |
Department of Signal Processing |
| fullinstit |
Ústav teorie informace a automatizace AV ČR, v. v. i. |
|
| source |
|
| cas_special |
| project |
| project_id |
7H14004 |
| agency |
GA MŠk |
| country |
BE |
| ARLID |
cav_un_auth*0306850 |
|
| abstract
(eng) |
This application note describes the precompiled Vivado 2013.4 Kintex7 designs with the floating point EdkDSP accelerators and examples of use of basic communication and computation blocks used in the video processing and image processing applications. The MicroBlaze SoC design with the AXI bus is based on the Xilinx BIST (build in self-test) provided by Xilinx for the Kintex7 KC705 board and the Vivado 2014.3 design flow. The network HW controller is supporting 1Gbit/100Mbit/10Mbit standards with HW DMA and a SW stack based on the lwIP library described in the Xilinx application note XAPP1026. The MicroBlaze processor is controlling 8 EdkDSP floating point accelerators. Each accelerator is organised as 8xSIMD reconfigurable data path, controlled by a PicoBlaze6 controller. This evaluation package is provided by UTIA for the Xilinx KC705 board with the 28nm Kintex7 xc7k325t-2 FPGA part. |
| reportyear |
2015 |
| RIV |
JC |
| permalink |
http://hdl.handle.net/11104/0242036 |
| confidential |
S |
| arlyear |
2014 |
| mrcbU10 |
2014 |
|