bibtype L - Prototype, methodology, f. module, software
ARLID 0451496
utime 20240103211318.1
mtime 20151201235959.9
title (primary) (eng) Evaluation of Asymmetric Multiprocessing for Zynq System-on-Modules TE0720-02-2IF, TE0720-02-1CF, TE0720-02-1QF with Carrier Board TE0701-05
publisher
pub_time 2015
keyword FPGA
keyword floating-point accelerator
keyword asymmetric multiprocessing
keyword ZYNQ Processing System
author (primary)
ARLID cav_un_auth*0101120
name1 Kadlec
name2 Jiří
full_dept (cz) Zpracování signálů
full_dept (eng) Department of Signal Processing
department (cz) ZS
department (eng) ZS
institution UTIA-B
full_dept Department of Signal Processing
fullinstit Ústav teorie informace a automatizace AV ČR, v. v. i.
author
ARLID cav_un_auth*0101179
name1 Pohl
name2 Zdeněk
full_dept (cz) Zpracování signálů
full_dept Department of Signal Processing
department (cz) ZS
department ZS
institution UTIA-B
full_dept Department of Signal Processing
fullinstit Ústav teorie informace a automatizace AV ČR, v. v. i.
source
url http://sp.utia.cz/index.php?ids=results&id=emc2_amp_on_zynq_trenz_2015_2
cas_special
project
project_id 7H14005
agency GA MŠk
country BE
ARLID cav_un_auth*0308433
abstract (eng) This application note describes the asymmetric multiprocessing design (AMP) based on the Xilinx application note XAPP1093. The AMP design is ported from ISE 14.5 design flow to the Xilinx Vivado 2015.2 and SDK 2015.2 design flow. The ARM Cortex A9 processor works together with the MicroBlaze processor, sharing the terminal and block ram. Both processors execute program from the same external DDR3 memory. The MicroBlaze processor is controlling 4 EdkDSP floating point accelerators. Each accelerator is organised as 8xSIMD reconfigurable data path, controlled by the PicoBlaze6 controller.
reportyear 2016
RIV JC
permalink http://hdl.handle.net/11104/0252656
confidential S
arlyear 2015
mrcbU10 2015